Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
A secure embedded operating system for microcontrollers
A simple RISC-V operating system written in Rust, written for learning purposes.
A fast, modern package manager for Static Binaries, Portable Formats (AppImage|AppBundle|FlatImage|Runimage) & More [maintainer=@QaidVoid]
64-bit RISC-V SoC emulator, cli and browser; boots Debian and more
Miralis is a RISC-V firmware that virtualizes RISC-V firmware
A lightweight Type-1 hypervisor for RISC-V H-extension, featuring RISC-V extension emulation. (on Milk-V Megrez)
First Prize in CSCC OS Competition 2025. Linux Compatible Operating System Kernel. 2025年全国大学生计算机系统能力大赛OS内核实现赛道一等奖作品
Toy microkernel and userspace written in Rust, exploring modern ideas
Minimal RISC-V core implementation (RV32IMA) for fun and learning
Cycle-accurate simulator of a RISC-V core
STARK proof system developed by Ciphercurve