Linux RISC-V virtual machine, powered by the Cartesi Machine emulator, running in the browser via WebAssembly
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risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 200 public repositories matching this topic...
Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809, XTMax
apple2 atari2600 z80 commodore-64 motorola-68000 6502 risc-v 8088 8051 z80-emulator intel-8086 8086 pcjr 68000 commodore64 pcxt 6809 eprom-emulator nabu 8051-microcontroller
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RISC Zero is a zero-knowledge verifiable general computing platform based on zk-STARKs and the RISC-V microarchitecture.
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Extendable Translating Instruction Set Simulator
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Speech-to-text, text-to-speech, speaker diarization, speech enhancement, source separation, and VAD using next-gen Kaldi with onnxruntime without Internet connection. Support embedded systems, Android, iOS, HarmonyOS, Raspberry Pi, RISC-V, RK NPU, Ascend NPU, x86_64 servers, websocket server/client, support 12 programming languages
android windows macos linux lazarus raspberry-pi ios text-to-speech csharp cpp dotnet speech-to-text aarch64 mfc risc-v object-pascal asr arm32 onnx vits
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C++ Instruction Set Simulator for RISC-V RV32IMC & custom SIMD instructions with cache and branch predictor models, C/ASM workloads, and Python analysis tools
emulator cache simd riscv performance-visualization performance-analysis risc-v instruction-set-simulator cache-simulator baremetal branch-prediction coremark rv32i branch-predictor dhrystone rv32im rv32imc riscv-emulator dpi-c embench
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The official repository for the gem5 computer-system architecture simulator.
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Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
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Nov 11, 2025 - C++
Unicode routines (UTF8, UTF16, UTF32) and Base64: billions of characters per second using SSE2, AVX2, NEON, AVX-512, RISC-V Vector Extension, LoongArch64, POWER. Part of Node.js, WebKit/Safari, Ladybird, Chromium, Cloudflare Workers and Bun.
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Template for fixed-point operations with a simplified math library (dedicated for RISC-V IM).
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Nov 10, 2025 - C++
RISC-V CPU simulator for education purposes
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Nov 13, 2025 - C++
Fast, modern C++ DSP framework, FFT, Sample Rate Conversion, FIR/IIR/Biquad Filters (SSE, AVX, AVX-512, ARM NEON, RISC-V RVV)
audio cplusplus dft cxx dsp cpp14 avx clang simd header-only fast-fourier-transform cpp17 cplusplus-14 fft digital-signal-processing avx512 risc-v audio-processing cplusplus-17 discrete-fourier-transform
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Nov 6, 2025 - C++
The fastest RISC-V sandbox
emulator lightweight multi-platform cmake interpreter cpp jit riscv low-latency zero-dependency no-dependencies userspace risc-v binary-translation cpp20 ultra-low-latency riscv-emulator
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A graphical processor simulator and assembly editor for the RISC-V ISA
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Open source ISS and logic RISC-V 32 bit project
linux c-plus-plus fpga processor iss embedded-systems verilog cpu-model risc-v soft-core 32-bit risc-processor co-simulation
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