SystemVerilog RISC-V RV32I_Zmmul 5-stage single-issue CPU core with branch predictor and L1 caches, tied up with ISA sim over DPI for verification

Processing Unit with RISCV-32 / RISCV-64 / RISCV-128

Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.

VeeR EL2 Core

Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128

System on Chip with RISCV-32 / RISCV-64 / RISCV-128

A highly-configurable RISC-V Core

Area & Power optimized RISC-V (RV32I) core with novel In-Register-File Computing (ACE-RF) architecture, implemented in SystemVerilog

A compact SystemVerilog SoC implementing a RV32IM CPU with memory‑mapped GPIO, UART and Timer peripherals on a Wishbone bus. Instruction memory is JTAG‑programmable and the repo includes Verilator testbenches plus a gcc-based toolchain to build C programs and generate Verilog‑readable instruction images.

Superscalar dual-issue RISC-V processor

This project is a final project in my master studies and it's done in a team of 2 people, Petar Stamenkovic and myself.

forked tiny tapeout tracable riscV soc with build and sim environments. I've integrated a nist800-232 cipher adding control and dma in systemverilog with tests in C.

A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in SystemVerilog. Stage 1, the purpose is to learn how to design a risc-v processor with basic peripherals and the RISC-V instruction set architecture.

LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.

2-way Out of Order RISC-V Processor

Python-based simulator for a 24-bit RISC processor with a five-stage pipeline. Focused on instruction-level, cycle-accurate modeling.

rv64/32i core

Garuda: Swift RISC-V INT8 accelerator for neural network inference. CVXIF coprocessor for CVA6 achieving 2-5x speedup.

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

RISCape is a 5-stage pipelined RISC-V processor