PolarFire SoC Discovery Kit Product Page

32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.

RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.

A single-cycle RISC-V CPU implementation in Logisim

Пример проекта с использованием make-файла для разработки приложений для микроконтроллера MIK32 - Микрон.

Processes a single 32-bit instruction in a single clock cycle. Based on the RISV-32 ISA supporting addition, subtraction, bitwise AND & OR operations. Based on the Harvard Architecture and Single-Cycle Microarchitecture

VM-RV32 is a virtual machine that emulates the RISC-V 32-bit ISA. It includes 64 detailed tutorials and supports meta-syntax for assertion expressions and printing to inspect registers and memory locations.

Jia_hao-risc-v-CPU v2.0: Upgrading from single-cycle to a 5-stage pipelined architecture with full data & control hazard resolution.

A simple risc-v single-core CPU design written in Verilog, developed for learning and practicing computer architecture and hardware description languages.

⚙️ AxonOS é um sistema operacional leve e customizado, desenvolvido do zero para rodar nativamente no SoC RISC-V.

Logic Synthesis QOR study, the best and worst case for hold and setup