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rtl

Here are 27 public repositories matching this topic...

chili-chips-ba / openCologne-PCIE

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypted, free SVerilog RTL with best-in-class VIP, Slot and M.2 cards for GateMate, the project opens PCIE connectivity to FPGAs, ASICs, I/O, acceleration, AI.

acceleration asic ai fpga simulation pipe pcb vip rtl verilog endpoint m2 pcie

Updated Apr 6, 2026
C++

thoughtworks / hardposit-chisel3

Chisel library for Unum Type-III Posit Arithmetic

scala chisel rtl chisel3 firrtl verilog floating-point posit unum fpu

Updated Apr 2, 2025
C++

ollycassidy13 / ReducedLUT

A tool for compression of lookup tables and generation of their hardware files in Verilog for RTL designs

compression fpga neural-network rtl verilog hardware-acceleration lookup-table ip-generation rtl-generation table-size-reduction hardware-ip

Updated Mar 30, 2025
C++

kiabuzz / CompressedLUT

A tool to generate optimized hardware files for univariate functions.

hls rtl hardware-acceleration lookup-table lossless-compression ip-generation function-evaluation table-size-reduction table-based-function-implementation function-implementation hardware-ip

Updated Apr 5, 2024
C++

gatery

synogate / gatery

Gatery, a library for circuit design.

library asic fpga cpp rtl vlsi vlsi-design rtl-design gatery

Updated Dec 9, 2024
C++

ShaheerSajid / RISCV

32-bit soft RISCV processor for FPGA applications

fpga processor embedded-systems riscv rtl ip verilog peripherals uart avalon risc-v verilator rv32imf

Updated Nov 25, 2023
C++

liang-aquarius / ca_model

A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are coming.

simulator cpp hardware rtl

Updated Sep 5, 2019
C++

ollycassidy13 / CompressedLUT

A tool to generate optimized hardware files for univariate functions.

fpga rtl hardware-acceleration lookup-table lossless-compression function-evaluation table-size-reduction table-based-function-implementation function-implementation

Updated Sep 5, 2024
C++

pytec8800 / pint_iverilog

Project PLS is developed based on icarus iverilog and will compile verilog into a much faster optimized model.

simulation rtl risc-v iverilog

Updated Nov 15, 2021
C++

liaoyunkun / RDMA-NIC-Isolation-Research

rtl rdma gem5-simulator

Updated Nov 11, 2025
C++

sean-galloway / RTLDesignSherpa

This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

rtl system-verilog dma crossbar cocotb amba-axi amba-apb fabric-generator

Updated Apr 16, 2026
C++

nhatpse / Deauther-RTL8720DN-ESP32S3

WiFi deauthentication tool for ESP32S3 and RTL8720DN supporting both 2.4GHz and 5GHz bands. Educational and penetration testing purposes only.

esp32 rtl iot-application

Updated Jan 27, 2026
C++

chili-chips-ba / openeye-CamSI-ethernet

1GigE UDP uplink of the live, real-time camera video stream. Think of it as Webcam-over-Ethernet, or RemoteCam. Great for security apps, this is a component of our 'openeye-CamSI' project that may also be used independently. It is fully operational and open for porting to your projects. Enjoy!

python opencv gui qt video fpga camera cpp udp rtl verilog vlc numphy

Updated Dec 9, 2025
C++

can-lehmann / hdl.cpp

Register-transfer Level Intermediate Representation

fpga cpp rtl verilog intermediate-representation

Updated Mar 17, 2026
C++

Archfx / sweetRV

sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA

firmware rtl hardware-designs risc-v riscv32

Updated May 13, 2024
C++

oscar7070 / RTLScript

RTLScript - type in Arabic, Hebrew, Farsi, and Urdu in C++ programs and get a fixed version of it!(forked from FarsiType)

unicode cxx cpp text utf-8 rtl bidirectional bidi arabic hebrew utf8 farsi urdu parsi tashkil rtlscript

Updated Jan 8, 2026
C++

synogate / gatery_template

Template project for using gatery

asic fpga cpp rtl vlsi vlsi-design rtl-design gatery

Updated Oct 17, 2024
C++

poshtkohi / psml

PSML: parallel system modeling and simulation language for electronic system level

Updated Feb 25, 2023
C++

ollycassidy13 / RandomInsertion

This program inserts random values into a lookup table (LUT) at positions identified as "don't cares" and generates a synthesizable Verilog file.

fpga neural-network rtl verilog

Updated Oct 22, 2024
C++

tom-johnsen / metalfpga

GPU hardware simulation on Apple GPUs: Verilog‑2005 frontend and Metal (MSL) backend that elaborates designs and emits Metal kernels/host runtime + VCDs.

macos metal compiler gpu eda rtl verilog codegen msl hdl vcd hardware-simulation apple-silicon metal-shading-language verilog-2005

Updated Jan 14, 2026
C++

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