How to build Zylin ZPU's GCC toolchain with Windows WSL 2022

The Zylin ZPU

Implementation of MIPS Processor Modules Using Verilog

16-bit MIPS Processor from scratch in VHDL

Soft-core RISC-V CPU

SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.

Soft core with support for the AVR8 instructions on verilog

A study of soft-core CPUs for use with FPGA designs

Trying to implement a soft core SoC

RISC-V processor in compliance with RV32IMZicsr

Uzh compiler

🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

LatticeMico32 instruction set simulator project

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

A fully automated, custom CPU and software stack for tiny embedded systems

Basic UART TX/RX module for FPGA

An open-source 32-bit RISC-V soft-core processor

Open source ISS and logic RISC-V 32 bit project

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.