This PR cleans up the FPGA timing flow so that Vivado reports the real critical paths instead of being dominated by non-functional timing violations.

In particular, it:

• rewrites the common JTAG/DMI CDC constraints to constrain the actual CDC boundaries instead of downstream consumer logic
• simplifies the common sync constraints to avoid parser-fragile Tcl constructs and reduce interference with the JTAG/DMI paths
• makes the FPGA core clock configurable from a single build parameter and propagates it consistently to Vivado and FPGA software builds
• align Pynq-Z2 and Nexys with the other Xilinx FPGA clocking flows by switching the clk_wiz input to board interfaces, updating the wrapper connections, and removing manual system clock constraints
• Simplify the Xilinx clock wizard configuration across FPGA targets by dropping derived auto-generated parameters and keeping only the board interface and intentional clock settings

The main goal is to mask the non-real timing violations that were previously polluting the reports. Before these changes, Vivado was spending attention on artificial CDC/debug paths that do not represent the actual performance limit of the design. After this cleanup, the timing reports expose the real bottlenecks.

With these fixes in place, the maximum synthesizable frequency without timing violations is now approximately:

• 40 MHz on ZCU104
• 25 MHz on Pynq-Z2

This makes the timing results much more meaningful and gives a realistic basis for future RTL optimization work.