SystemVerilog (IEEE 1800-2017) Simulator

draws an SVG schematic from a JSON netlist

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design. Documentation is here:

Blender GDSII Importer with PDK Support

LLM-Assisted Hardware Formal Verification Tool

Memory protected microkernel realtime operating system for microcontrollers without MMU.

GUI for gds2palace RFIC FEM simulation worklow

PACT: A Parallel Compact Thermal Simulator

Hardened RISC-V core

Static RTL Fault Injection

An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️

[WIP] Open-source DFT flow

This repository contains source code that is aimed at converting a Spice NetList to its corresponding layout.

A custom C++ routine to identify logic gates in the layout extracted netlist (SPICE) of digital circuits and generate gate-level Verilog netlist, in the presence of logic gate defintions from the s…

Open-source repository for a standard-cell library characterizer using complete open-source tools

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

design and verification of asynchronous circuits

RISC-V Formal Verification Framework

Side-Channel Analysis Library

HAL – The Hardware Analyzer

Verilator open-source SystemVerilog simulator and lint system

Course material for a basic hands-on analog circuit design course with IC emphasis

Dear ImGui: Bloat-free Graphical User interface for C++ with minimal dependencies

A curated list of awesome C++ (or C) frameworks, libraries, resources, and shiny things. Inspired by awesome-... stuff.

A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.

VHDL compiler and simulator

RISC-V based student processor for embedded applications.