dude, is my code constant time?

Python control library for the Faultier fault-injection tool.

Post-quantum crypto library for the ARM Cortex-M4

SCAbox's website

Implementation of NPcVAE-OSM model introduced in "From linear regression to generative model for explainable non profiled side-channel attacks" article

CryptoBAP: Automated Side-Channel Analysis of Cryptographic Protocols Implementations

Exploiting the Semantic Gap in Trusted Execution Environments

A curated list of public TEE resources for learning how to reverse-engineer and achieve trusted code execution on ARM devices

A Huge Learning Resources with Labs For Offensive Security Players

Lab about a cache-timing attack on fast software AES encryption. Based on "Cache-timing attacks on AES" by Daniel J. BERNSTEIN. Test performed on Raspberry Pi 4 board.

An step by step fuzzing tutorial. A GitHub Security Lab initiative

Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)

A Rust library for finite-field arithmetic, elliptic-curve operations, isogeny scaffolding, and higher-level elliptic-curve protocols.

Machine-readable data describing Arm architecture and implementations. Includes JSON descriptions of implemented PMU events.

🍨 Soothing pastel theme for Neovim

🦀🌡️ Real-time system monitor for Apple Silicon Macs (M1–M5). No sudo. TUI, JSON/Prometheus metrics server, and Rust library.

Repository of experiment for the paper

Vulnerability detection framework by Binarly's REsearch team

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Chat client on an LLC covert channel

Hands on with side-channels: a tutorial on covert-channels built using shared CPU resources. Three different covert-channel implementations based on Flush+Reload and Prime+Probe (L1, LLC) side-chan…

Student Starter Code for Secure Hardware Design at MIT

Prime+Count: A Novel Cross-world Covert Channel on ARM TrustZone

A collection of links related to Linux kernel security and exploitation

Using Data Memory-Dependent Prefetchers to Leak Data at Rest

Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)

Synchronization Storage Channels (S2C): Timer-less Cache Side-Channel Attacks on the Apple M1 via Hardware Synchronization Instructions -- USENIX Security'23