The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated

Systolic-array based Deep Learning Accelerator generator

RTL, Cmodel, and testbench for NVDLA

synthesiseable ieee 754 floating point library in verilog

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…

Full Support 32bit RISC-V in LLVM and CLANG for Vector Extension

This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.

AES RoCC Accelerator

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.

Chisel components for FPGA projects

关于RISC-V你所需要知道的一切

通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using github issue and markdown! (inculding Machine Learning algs …

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Working draft of the proposed RISC-V V vector extension

RISC-V Instruction Set Manual

Vector processor for RISC-V vector ISA

A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)