Tags: olajep/oh

parallealla/fpga: Rewrite Makefiles's to use quiet.mk

Better output

Signed-off-by: Ola Jeppsson <ola.jeppsson@gmail.com>

spi: spi_master_io: Add 1 cycle grace period between transfers

Ensure that SS=1 for at least one SCLK clock cycle between transfers.
Fixes race condition where the slave misses the end of transfer signal.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>

Merge pull request aolofsson#63 from olajep/e16-z7010-headless

E16 z7010 headless

Merge pull request aolofsson#63 from olajep/e16-z7010-headless

E16 z7010 headless

Merge pull request aolofsson#63 from olajep/e16-z7010-headless

E16 z7010 headless