Stars
ICRTL Benchmark: Industrial-level RTL design challenges for evaluating PPA optimization, code generation, and LLM applications in EDA.
A comprehensive benchmark for AI-aided chip design
The open alternative to Salesforce, designed for AI.
Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Dr.RTL: Autonomous Agentic RTL optimization through Tool-Grounded Self-Improvement
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
Compiler Explorer for RTL: synthesize Verilog with Yosys and explore timing paths, logic depth, and fanin/fanout interactively
Lightweight coding agent that runs in your terminal
LEAKED SYSTEM PROMPTS FOR CHATGPT, CLAUDE, GEMINI, GROK, PERPLEXITY, CURSOR, LOVABLE, REPLIT, AND MORE! - AI SYSTEMS TRANSPARENCY FOR ALL! 👐
V-Mate is a RISC V core processor developed by Hu-mind.AI VLSI Teammates tool.
Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.
Modular hardware build system
HARC: verification language compiler, sister to ARCH
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Condor Computing's fork of Spike with STF and BBV support, Spike-STF
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
ASIC implementation flow infrastructure, successor to OpenLane
Digital HDL Design Full-stack Agents