Lists (5)
Starred repositories
Library for reducing tail latency in RAM reads
SystemVerilog compiler and language services
The TinyLlama project is an open endeavor to pretrain a 1.1B Llama model on 3 trillion tokens.
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first …
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
A description of Minotaur can be found in https://arxiv.org/abs/2306.00229.
RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
An app that brings language models directly to your phone.
Use ESP8266 and NRF24L01+ as a wireless Logitech Unifying keyboard/mouse
Real-time microphone noise suppression on Linux.
The testing ground for the future of portable SIMD in Rust
Manas project aims to create a modular framework and ecosystem to create robust storage servers adhering to Solid protocol in rust.
Home of test harnesses used in LTT Labs MarkBench
Enhanced ChatGPT Clone: Features Agents, MCP, Skills, DeepSeek, Anthropic, AWS, OpenAI, Responses API, Azure, Groq, o1, GPT-5, Mistral, OpenRouter, Vertex AI, Gemini, Artifacts, AI model switching,…
Portable Packed SIMD Vectors for Rust standard library
A Linux-capable RISC-V multicore for and by the world
PypelineC: A hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Test/benchmark regression and comparison system with dashboard