GitHub - cominixo/verileste: WIP port of Celeste Classic to Verilog · GitHub

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
rtl		rtl
.gitignore		.gitignore
Makefile		Makefile
inputs.mem		inputs.mem
is_solid.mem		is_solid.mem
is_solid_generator.py		is_solid_generator.py
tb.sv		tb.sv
verileste.cst		verileste.cst

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WIP port of Celeste Classic to Verilog

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