Illegal rust

Visualize, query, and stream to train on multimodal robotics data.

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

Scala based HDL

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Rules for performing tasks related to FPGA development in Bazel.

a SocketCAN over Ethernet tunnel

A process for automating Docker container base image updates.

A SWD programmer for ARM Cortex microcontrollers.

MicroShell is a lightweight pure C implementation of shell emulator dedicated for embedded bare-metal systems.

Interactive visualization and analytics on ADS-B data with ClickHouse

A CMSIS-SVD file parser

CMSIS-SVD tools

Scripts and templates for assisting development. Code generators, MMIO Register interfaces.

Generated C++ code for accessing SiFive's peripherals

Xilinx virtual cable server for generic FTDI 4232H.

C++ Standard Lib adapted to embedded environments

A safe and fast high-level and low-level character input/output library for bare-metal and RTOS based embedded systems with a very small binary footprint.

Portable Bitfields implementation, with configurable behavior.

Shell for Small Embedded Devices based on microrl

Micro Read Line library for small and embedded devices [REMASTER]

Script for analyzing ELF memory usage

Sample minimal Vivado project for Parallella FPGA

🌊 Digital timing diagram rendering engine

Yosys Open SYnthesis Suite

experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.

The Elixir Cross Referencer

Intrepid Control Systems device communication library

Tiny, fast(ish), self-contained, fully loaded printf, sprinf etc. implementation; particularly useful in embedded systems.