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MiST Minimig AGA core for IcePi Zero and FleaFPGA Ohm Lattice ECP5 boards

Verilog 6 Updated Aug 13, 2026

Use an ULX3s FPGA to emulate an Atari ST cartridge

Verilog 2 Updated Jun 25, 2026

Repo containing random docs, details and other assets generated using Claude Code / claude.ai to help with replacing the proprietary BMC on Dell C410X and Supermicro X11 motherboards.

C 3 Updated Jul 22, 2026

FPGA SoC learning project: soft RISC-V CPU, Linux, and hardware-accelerated int8 digit classification on a Radiona ULX3S

C 5 Updated Aug 4, 2026

An implementation of PowerVR2/CLX2 CORE

SystemVerilog 15 2 Updated Aug 12, 2026

Switchyard lets LLM applications route traffic across models and providers while preserving native OpenAI and Anthropic API compatibility - enabling flexible model selection, benchmarking, and cost…

Rust 1,300 115 Updated Aug 14, 2026

Production-grade engineering skills for AI coding agents.

JavaScript 87,045 9,349 Updated Aug 11, 2026

Firmware / software / Verilog for the Photon camera

Python 18 3 Updated Jul 12, 2026

dev tools, env vars, task runner

Rust 32,390 1,358 Updated Aug 14, 2026

An Amiga emulator written in Rust

Rust 97 10 Updated Aug 13, 2026

Zero-dependency C99 GPT-2 engine for edge AI. Sub-1M parameter models train on-device in seconds. Organelle Pipeline Architecture (OPA) coordinates specialised micro-models — 91% win rates on 11 lo…

C 113 9 Updated Jul 14, 2026

Use AI Agents directly in Blender.

Python 912 78 Updated May 26, 2026

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

Python 106 8 Updated Aug 13, 2026

Slint is an open-source declarative GUI toolkit to build native user interfaces for Rust, C++, JavaScript, or Python apps.

Rust 23,453 953 Updated Aug 13, 2026

IRC application written in Rust

Rust 4,398 210 Updated Aug 14, 2026

The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With standard PIPE interface for vendor SerDes. Portable, unencrypte…

C++ 79 6 Updated Jul 11, 2026

Using a soft CPU on FPGA to interface USB 1.1 FS devices, including Xbox 360 wireless/wired controllers

Verilog 7 Updated Oct 30, 2024

Interactive study + AI-powered interview practice tool for .NET 8 core AI Engineer interview topics.

JavaScript 15 4 Updated May 12, 2026

Lightweight coding agent written in Rust, optimized for memory footprint and performance

Rust 1,573 122 Updated Aug 12, 2026

The cryptography-based networking stack for building unstoppable networks with LoRa, Packet Radio, WiFi and everything in between.

Python 6,809 500 Updated Jul 26, 2026

Observal is a local registry and analytics platform for your AI components. Setup Observal, define the scope and share your Skills, MCPs and Agents.

Python 2,358 472 Updated Aug 12, 2026

Fast, powerful, git-native ticket tracking in a single bash script. Dependency graphs, priority levels, zero setup.

Shell 858 61 Updated Mar 16, 2026

Apple II DOS 3.3 6-and-2 GCR codec in SystemVerilog (nibbler + denibbler) with Python golden reference and Verilator testbenches

SystemVerilog 1 Updated May 12, 2026

Open-source, community-driven agent harness

Rust 40,772 3,522 Updated Aug 14, 2026

🤗 ml-intern: an open-source ML engineer that reads papers, trains models, and ships ML models

Python 10,725 1,169 Updated Jul 30, 2026

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

VHDL 69 7 Updated Feb 16, 2026

PCIe stack written in Amaranth.

Python 17 1 Updated Apr 27, 2026

Repo containing an AI generated report on the status of open source PCIe implementations (for FPGAs).

7 Updated Oct 15, 2025

🎧 Your Personal Streaming Service

Go 22,868 1,631 Updated Aug 14, 2026
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