Package manager and build abstraction tool for FPGA/ASIC development

Inference Llama 2 in one file of pure C

Greyhound on IHP SG13G2 0.13 μm BiCMOS process

ASIC implementation flow infrastructure, successor to OpenLane

Netlist API (and more) for EDA flow development

AXI, AXI stream, Ethernet, and PCIe components in System Verilog

Verilog Ethernet components for FPGA implementation

The Panamax 130-pin padframe for SkyWater sky130

A Fully Open-Source Verilog-to-PCB Flow

PicoRV32 - A Size-Optimized RISC-V CPU

SERV - The SErial RISC-V CPU

Work in progress distributed system that simplifies the orchestration of containers and virtual machines.

Libelf is a simple library to read ELF files.

Build your hardware, easily!

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Linsn RV901T HUB75 LED "Receiver Card" Reverse Engineering

Complete flight control system designed from scratch. Hardware designed with KiCad.

Set of advanced samples for the NVIDIA OptiX Ray Tracing Engine.

Course materials for Modern Binary Exploitation by RPISEC