A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code

Instruction Set Generator initially contributed by Futurewei

Instruction Set Generator initially contributed by Futurewei

RISC-V SoC designed by students in UCAS

Formal verification on NutShell using riscv-spec-core

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Spike, a RISC-V ISA Simulator

Vector processor for RISC-V vector ISA

Top project for RISC-V Matrix extension proposal and related opensource implementations.

Open-source high-performance RISC-V processor

OpenXuantie - OpenC910 Core

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…

espresso logic minimizer (https://embedded.eecs.berkeley.edu/pubs/downloads/espresso/index.htm)

VeeR EH2 core

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

CVA6 SDK containing RISC-V tools and Buildroot

Ariane is a 6-stage RISC-V CPU

Wrapper for ETH Ariane Core

lzbench is an in-memory benchmark of open-source compressors

A fast compressor/decompressor

Zstandard - Fast real-time compression algorithm

Unofficial clone of SESC. Builds with modern C++ compilers.