How to read Lean

My color settings for Lean 4 in VS Code

Dynamic analysis framework for .NET programs

Kimina Lean server (+ client SDK)

Hardware, Linux Driver and Library for the Zynq AXI DMA interface

SHA256 hardware accelerator, synthesized for and mapped on the Zynq core of the Zybo board by Digilent

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

An English translation of Grothendieck's Fondements de la Géometrie Algébrique

Blueprint for the PNT+ Project

A modern hardware definition language and toolchain based on Python

Lean 3's obsolete mathematical components library: please use mathlib4

Standard HyperRAM core for ECP5 written in Litex/Migen

A few basic designs to demonstrate the syntax for using nMigen's basic features.

Bluetooth PHY based on one-bit input and output

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Homebrew game for homebrew FPGA game console

Yosys Open SYnthesis Suite

Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

A collection of small eagle PCB designs

SoC based on VexRiscv and ICE40 UP5K

Simple machine mode program to probe RISC-V control and status registers

Public repository for Litefury & Nitefury

Public repository for PicoEVB (Xilinx Artix XC7A50T based)