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A translator from Intel SSE intrinsics to Arm/Aarch64 NEON implementation

C++ 1,515 232 Updated Apr 12, 2026

A "device memory" enabling project encompassing tools and libraries for CXL, NVDIMMs, DAX, memory tiering and other platform memory device topics.

C 321 146 Updated Jun 16, 2026

OpenXuantie - OpenC906 Core

Verilog 405 124 Updated Jun 28, 2024

Pond: CXL-Based Memory Pooling Systems for Cloud Platforms (ASPLOS'23)

HTML 227 45 Updated Oct 13, 2024

draft driver for pcie subsystem

C 1 4 Updated Nov 17, 2020

EDK II

C 6,061 3,179 Updated Jun 23, 2026

Docker image for Petalinux 2024.2

Dockerfile 4 1 Updated Feb 6, 2025

Books for PCIe and NVMe

1 1 Updated Aug 27, 2023

AXI4 Transactor and Bus Functional Model

VHDL 4 2 Updated Jul 17, 2014

AMBA bus generator including AXI4, AXI3, AHB, and APB

C 245 62 Updated Jul 16, 2023

Multi-GPU CUDA stress test

C++ 2,240 408 Updated May 31, 2026

PCIe Device Emulation in QEMU

C 95 28 Updated Mar 28, 2023

PCI_Express总线经典书籍

109 77 Updated May 13, 2022

LitePCIe PTM support / test repo.

Python 10 2 Updated Oct 15, 2024

On-chip logic analyzer for FPGAs

C 4 2 Updated Nov 27, 2017

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

Verilog 35 5 Updated Oct 15, 2018

单片机APP程序

C++ 530 173 Updated Mar 25, 2021

24 channel, 100Msps logic analyzer hardware and software

Python 4,827 519 Updated Feb 11, 2026

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Verilog 173 21 Updated Jun 24, 2021

OLS is a $50 32 channel Logic Analyzer

Java 125 36 Updated Jul 25, 2011

Lightning Fast Serialization of Data Frames for R

R 626 43 Updated Sep 26, 2024

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage …

C 31 10 Updated Oct 18, 2018

An open source multi-function instrument for everyone

Python 1,391 501 Updated Nov 5, 2024

Home of the Advanced Interface Bus (AIB) specification.

61 8 Updated Aug 30, 2022

An Open Source Link Protocol and Controller

Verilog 29 8 Updated Aug 1, 2021

1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)

Verilog 24 16 Updated Jul 17, 2014

Linux device driver for dma buffer using dma_alloc_coherent()

C 4 5 Updated Jul 17, 2015

User space mappable dma buffer device driver for Linux.

C 692 188 Updated Mar 12, 2026

NVMe management command line interface.

C 1,798 719 Updated Jun 22, 2026
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