Stars
Superscalar OoO RISC-V CPU, marchid: 50 (0x32).
100Mbps unmanaged cut-through ethernet switch.
A VVC/H.266 screen content encoder in hardware and software.
Node module that generates byte field diagrams in SVG format
Library for reducing tail latency in RAM reads
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
基于高云FPGA与AD9363/AD9361射频收发器，构建了一套灵活可重构的软件无线电（SDR）系统，通信核心代码纯Verilog实现。软硬件全开源，高速基带处理部署于FPGA，交互业务部署于Python上位机，通过千兆以太网交互，实现了QPSK等多种实时通信与动态参数配置 Based on the Gowin FPGA and AD9363/AD9361 RF transceiver, …
Open-source, low-cost 10.5 GHz PLFM phased array RADAR system
Open-source 4in1 AM32 ESC for FPV drones. 20x20 mounting, 6S, AT32F421 per channel. KiCad 10, CERN-OHL-S-2.0.
reading the undocumented mems accelerometer + gyroscope on apple silicon macbooks via iokit hid
UDP-IP stack accelerator and is able to send and receive data through Ethernet link
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …
Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-Stream.
Software defined radio receiver powered by GNU Radio and Qt.
Updated FPGA source code and binaries for UHD B220 Clone with XC7A200T+AD9361
Bluespec translator for surfer waveform viewer.
Scalable Interface for RISC-V ISA Extensions
A computer science textbook
A Dockerized python Script to fetch Garmin health data and populate that in a InfluxDB Database, for visualization long term health trends with Grafana
A machine learning accelerator core designed for energy-efficient AI at the edge.