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29th VLSI Design 2016: Kolkata, India
- 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, VLSID 2016, Kolkata, India, January 4-8, 2016. IEEE Computer Society 2016, ISBN 978-1-4673-8700-2
Tutorials
- Jacob A. Abraham, Abhijit Chatterjee:
Design of Self Calibrating and Error Resilient Mixed-Signal Systems for Signal Processing, Communications and Control. 1-2 - Swagath Venkataramani, Kaushik Roy, Anand Raghunathan:
Approximate Computing. 3-4 - Nikil D. Dutt
, Nima Taherinejad:
Self-Awareness in Cyber-Physical Systems. 5-6 - Neel Gala, Arjun Menon, Rahul Bodduna, G. S. Madhusudan, V. Kamakoti:
SHAKTI Processors: An Open-Source Hardware Initiative. 7-8 - Kanad Basu, Subhadip Kundu:
Post-Silicon Validation and Diagnosis. 9-10 - Kewal K. Saluja:
Digital Testing - Basics to Advanced Research Issues. 11 - Sandip Kundu, Omer Khan:
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. 12-13 - Nilanjan Mukherjee, Janusz Rajski:
Digital Testing of ICs for Automotive Applications. 14-16 - Shanthi Pavan, Nagendra Krishnapura:
Demystifying Time Varying Circuits and Systems. 17-18 - Anuradha Annaswamy, Samarjit Chakraborty, Dip Goswami, S. Ramesh, Marilyn Wolf:
Trustworthy Cyber Physical Systems. 19-20 - Adit D. Singh:
Adaptive Test Methods for High IC Quality and Reliability. 21-22 - Ingrid Verbauwhede
Embedded Security. 23 - Susanta Sengupta:
RF System Design of an RFIC Receiver for IoT. 24 - Zoran Stamenkovic:
SOC Design for Wireless Communications. 25 - Kausik Datta, Goutam Kumar Bhaumik, Rohit Goel:
An Introduction to VHDL 2008. 26-27 - Gaurav Saharawat, Praveen Shukla, Saurabh Jain, Subash Nayak:
Emulation - Smart Way of Power Estimation and Power Aware Verfication. 28-29 - Sandeep K. Shukla:
Cyber Security of Cyber Physical Systems: Cyber Threats and Defense of Critical Infrastructures. 30-31
Embedded Tutorials
- Abhronil Sengupta, Priyadarshini Panda, Anand Raghunathan
Neuromorphic Computing Enabled by Spin-Transfer Torque Devices. 32-37 - Muralidharan Venkatasubramanian, Vishwani D. Agrawal:
Database Search and ATPG - Interdisciplinary Domains and Algorithms. 38-43 - Rolf Drechsler
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC. 44-49
Special Sessions
- Mark M. Tehranipoor:
New Directions in Hardware Security. 50-52 - Partha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani:
The Future of NoCs: New Technologies and Architectures. 53-55 - Samarjit Chakraborty, S. Ramesh:
Technologies for Safe and Intelligent Transportation Systems. 56-58 - Tsung-Yi Ho
Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences. 59-62
Networks on Chip (Session M/B-1)
- Tanya Shreedhar, Sujay Deb
Hierarchical Cluster Based NoC Design Using Wireless Interconnects for Coherence Support. 63-68 - Sonal Yadav, Vijay Laxmi
A Power Efficient Dual Link Mesh NoC Architecture to Support Nonuniform Traffic Arbitration at Routing Logic. 69-74 - Priyanka Mitra:
A Statistical Model for Hybrid Wireless Network on Chip. 75-80 - Wazir Singh
Energy Efficient and Congestion-Aware Router Design for Future NoCs. 81-85 - Sai Vineel Reddy Chittamuru
SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip. 86-91
Advances in Architecture (Session M/B-2)
- Shirshendu Das, Hemangee K. Kapoor:
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. 92-97 - Farhad Merchant
Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation. 98-103 - Ishan G. Thakkar, Sudeep Pasricha:
Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures. 104-109
Advances in Digital Design (Session T/C-1)
- Nazma Tara, Hafiz Md. Hasan Babu, Nawshi Matin:
Logic Synthesis in Reversible PLA. 110-115 - Mohd Anwar, Sourav Saha, Matthew M. Ziegler, Lakshmi N. Reddy:
Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis. 116-121 - Apoorva Pathak, Divyesh Sachan, Harish Peta, Manish Goswami:
A Modified SRAM Based Low Power Memory Design. 122-127 - Ritsuko Muguruma, Shigeru Yamashita:
Stochastic Number Generation with Few Inputs. 128-133 - Sunil Dutt, Harsh Patel, Sukumar Nandi
Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-Resilient Applications. 134-139 - M. Mohamed Asan Basiri
An Efficient VLSI Architecture for Discrete Hadamard Transform. 140-145
Analog/RF Design 1 (Session M/A-2)
- M. V. Prajwal, B. S. Srinivas, S. Shodhan, M. K. Jayaram Reddy, Tonse Laxminidhi:
A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier. 146-150 - Samiran Dam, Pradip Mandal:
A Stacked VCO Architecture for Generating Multi-level Synchronous Control Signals. 151-155 - Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner
A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology Mounted in BGA Package. 156-161 - Vinaya M. M., Roy Paily
Power Optimization of LNA for LTE Receiver. 162-167 - Manas Kumar Lenka, Akash Agrawal, Vishal Khatri, Gaurab Banerjee:
A Wide-Band Receiver Front-End with Programmable Frequency Selective Input Matching. 168-173
High Performance Analog for Digital Systems (Session T/A-1)
- R. G. Raghavendra, Balbeer Singh Rathor:
A 1-tap 10.3125Gb/s Programmable Voltage Mode Line Driver in 28nm CMOS Technology. 174-178 - Amit Chhabra, Vikas Rana:
-1.1V to +1.1V 3: 1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI. 179-184 - Anil Kumar Gundu, Mohammad S. Hashmi
A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications. 185-190 - Ashish Kumar, G. S. Visweswaran, Vinay Kumar, Kaushik Saha:
A 0.5V VMIN 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. 191-195 - Mahendra Sakare
A Quarter-Rate 27-1 Pseudo-Random Binary Sequence Generator Using Interleaved Architecture. 196-201 - A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. 202-206
Analog/RF Circuits for Communications (Session T/A-2)
- Sesha Sairam Regulagadda, Purushothama Chary, Rizwan Shaik Peerla, Mohd Abdul Naseeb, Amit Acharyya
A 1.5mA, 2.4GHz ZigBee/BLE QLMVF Receiver Frond End with Split TCAs in 180nm CMOS. 207-212 - Saurabh R. Anmadwar, Nandakumar Nambath
Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver. 213-218 - Badreyya Al Shehhi, Mihai Sanduleanu
An 800µW Peak Power Consumption, 24GHz (K-Band), Super-Regenerative Receiver with 200p J/bit Energy Efficiency, for IoT. 219-223 - Saroj Mondal
An Efficient on Chip Power Management Architecture for Solar Energy Harvesting Systems. 224-229 - Kamlesh Singh
A 14 Bit Dual Channel Incremental Continuous-Time Delta Sigma Modulator for Multiplexed Data Acquisition. 230-235 - Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak:
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. 236-239
Analog/RF Design 2 (Session W/A-1)
- Krishna Kanth Gowri Avalur, Syed Azeemuddin
System Efficiency Improvement Technique for Automotive Power Management IC Using Maximum Load Current Selector Circuit. 240-245 - Jos A. V. Prakash, Babita R. Jose, Jimson Mathew:
A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled Sigma-Delta Modulator. 246-251
Power Aware Design (Session M/C-1)
- Lokesh Garg, Vineet Sahula
Accurate and Efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits. 252-257 - Satyabrata Dash, Krishna Lal Baishnab, Gaurav Trivedi:
Applying River Formation Dynamics to Analyze VLSI Power Grid Networks. 258-263 - Hrishikesh Jayakumar
Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices. 264-269 - Lawrence M. Schlitt, Priyank Kalla, Steve Blair:
A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic Layouts. 270-275 - Ashish Kumar Pradhan, Soumitra Kumar Nandy:
An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO Communication. 276-281
Process Technologies and Advancements in Memory (Session M/A-1)
- Vishnuram Abhinav
A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach. 282-287 - Archana Pandey
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. 288-293 - N. B. Balamurugan
Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FET. 294-299 - Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha:
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. 300-305 - Sadulla Shaik
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing. 306-311
Device Modeling and Simulation (Session W/D-1)
- Dheeraj Kumar Sinha, Amitabh Chatterjee, Vishnuram Abhinav
A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET. 312-317 - Rajat Gupta, Vijit Gadi, H. Anirudh Upendar:
Write Assist Scheme to Enhance SRAM Cell Reliability Using Voltage Sensing Technique. 318-322 - Apoorva Ojha, Narendra Parihar, Nihar R. Mohapatra:
Analysis and Modeling of Stress over Layer Induced Threshold Voltage Shift in HKMG nMOS Transistors. 323-327 - Chandan Yadav, Anupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Yogesh Singh Chauhan
Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence. 328-333 - Rakesh Prasher, Devi Dass, Rakesh Vaid
Al/HfO2/Si Gate Stack with Improved Physical and Electrical Parameters. 334-337 - A. Anvar, Shreepad Karmalkar
A Quasi-Static Model for the Coupling Impedance between Coplanar Rectangular Contacts on a Bulk Substrate. 338-342
Emerging Technologies in Integrated Circuits and Healthcare (Session T/D-2)
- Sandeep Chandran
A Generic Implementation of Barriers Using Optical Interconnects. 349-354 - Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita:
ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips. 355-360 - Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain:
Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases. 361-366 - Naren Das
Nanostructured Silicon Oxide Immunosensor Integrated with Noise Spectroscopy Electronics for POC Diagnostics. 367-372
Emerging Trends in Digital IC Design (Session W/A-1)
- Shivam Swami, Kartik Mohanram:
E3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-volatile Memories. 373-378 - Arindam Banerjee, Debesh Kumar Das:
Squaring in Reversible Logic Using Zero Garbage and Reduced Ancillary Inputs. 385-390
Issues in Embedded System Design (Session W/B-1)
- Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan:
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. 391-396 - Jian Cai, Aviral Shrivastava
Software Coherence Management on Non-coherent Cache Multi-cores. 397-402 - Arnab Sarkar, Arijit Mondal:
Partitioned Fair Round Robin: A Fast and Accurate QoS Aware Scheduler for Embedded Systems. 403-408 - Vinay B. Y. Kumar
Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. 409-414 - Farhad Merchant
Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic. 415-420 - Vaddi Chandra Sekhar, Satyajit Bora, Monalisa Dash
Design and Implementation of Blind Assistance System Using Real Time Stereo Vision Algorithms. 421-426
FPGA-based Designs and Reconfigurable Architectures (Session M/C-2)
- Jubin Mitra, Shuaib Ahmad Khan, Rourab Paul
Error Resilient Secure Multi-gigabit Optical Link Design for High Energy Physics Experiment. 427-432 - Ayan Palchaudhuri
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. 433-438 - Saugata Datta, Kuruvilla Varghese, Shayan Garani Srinivasa:
A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. 439-444 - Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu:
An Improved Design of a Reversible Fault Tolerant LUT-based FPGA. 445-450 - Pradipta Roy, Prabir K. Biswas, Binoy Kumar Das:
A Modified Hill Climbing Based Watershed Algorithm and Its Real Time FPGA Implementation. 451-456 - Sangeetha Damotharasamy
An Efficient Hardware Implementation of Canny Edge Detection Algorithm. 457-462
New Test Generation Methods (Session T/B-2)
- Sabyasachi Deyati, Barry John Muldrey
TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. 463-468 - Vineeta Shukla, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin
Fault Modeling and Simulation of MEDA Based Digital Microfluidics Biochips. 469-474 - Rajit Karmakar, Santanu Chattopadhyay:
Thermal-Safe Schedule Generation for System-on-Chip Testing. 475-480
Reliability and Fault Tolerance (Session W/B-2)
- Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance through Invariant Checking for Iterative Solvers. 481-486 - G. Cardoso Medeiros, Letícia Maria Bolzani Pöhls, Fabian Vargas:
Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects. 487-492
Advances in Timing, Verification and Synthesis (Session T/B-1)
- Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma:
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. 493-498 - Vikas Chauhan, Neel Gala, V. Kamakoti:
ChADD: An ADD Based Chisel Compiler with Reduced Syntactic Variance. 499-504 - Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
An Efficient Method for Clock Skew Scheduling to Reduce Peak Current. 505-510 - William Lee, Tannu Sharma, Kenneth S. Stevens:
Path Based Timing Validation for Timed Asynchronous Design. 511-516 - Debjit Pal
Symptomatic Bug Localization for Functional Debug of Hardware Designs. 517-522
Technologies for Secure Embedded Circuits and Systems (Session T/C-2)
- Jeroen Bosmans, Sujoy Sinha Roy, Kimmo Järvinen, Ingrid Verbauwhede
A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime Field. 523-528 - Abhishek Chakraborty, Debdeep Mukhopadhyay:
A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVM. 529-534 - Urbi Chatterjee, Rajat Subhra Chakraborty, Jimson Mathew, Dhiraj K. Pradhan:
Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation. 535-540 - Jungmin Park, Akhilesh Tyagi:
Security Metrics for Power Based SCA Resistant Hardware Implementation. 541-546 - Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Vivekananda Vedula, Ramesh Karri
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. 547-552
Interactive Presentation Papers-1 (Session W/C-1)
- Pallavi Paliwal
A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop. 553-554 - Pragya Maheshwari, Suhas Kaushik, Mahendra Sakare
A 12.5 Gbps One-Fifth Rate CDR Incorporating a Novel Sampler Based Phase Detector and a DFE. 555-556 - Shouri Chatterjee
A 100-nW Sensitive RF-to-DC CMOS Rectifier for Energy Harvesting Applications. 557-558 - Abishek Thekkeyil Kunnath, Bibhudatta Sahoo:
A Digitally Assisted Radiation Hardened Current Steering DAC. 559-560 - Harsh N. Patel, Farah B. Yahya, Benton H. Calhoun:
Improving Reliability and Energy Requirements of Memory in Body Sensor Networks. 561-562 - Sudarshan Srinivasan, Nithesh kurella, Israel Koren, Sandip Kundu:
Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors. 563-564 - Sriram Sundaram, Sriram Sambamurthy, Michael Austin, Aaron Grenat, Michael Golden, Stephen Kosonocky, Samuel Naffziger:
Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. 565-566 - Syed Ershad Ahmed, S. Sweekruth Srinivas, M. B. Srinivas:
A Hybrid Energy Efficient Digital Comparator. 567-568 - Debashish Sahu, Siddhartha Hazra, Prajit Nandi:
Modeling of Linear Variable Differential Transformer. 569-570 - Chandan Yadav, Amit Agarwal, Yogesh Singh Chauhan
Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor. 571-572 - Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. 573-574 - Bibhash Sen, Rajdeep Kumar Nath, Rijoy Mukherjee, Yashraj Sahu, Biplab K. Sikdar
Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect. 575-576 - Shankarayya G. Kambalimath
FPGA-based Design of a Hearing Aid with Frequency Response Selection through Audio Input. 579-580 - Manchi Pavan Kumar, Roy Paily
Design and Implementation of Low-Power Digital Baseband Transceivers for IEEE802.15.6 Standard. 581-582 - Richa Mishra, Tarun Kanti Bhattacharyya, Tapas Kumar Maiti:
Design and Simulation of Microfluidic Components towards Development of a Controlled Drug Delivery Platform. 583-584 - Sikhar Patranabis, Debapriya Basu Roy, Debdeep Mukhopadhyay:
Using Tweaks to Design Fault Resistant Ciphers. 585-586 - Vinayaka Jyothi, Xueyang Wang, Sateesh Addepalli, Ramesh Karri
BRAIN: BehavioR Based Adaptive Intrusion Detection in Networks: Using Hardware Performance Counters to Detect DDoS Attacks. 587-588
Interactive Presentation Papers-2 (Session W/C-2)
- Sudhi Proch, Prabhat Mishra
Test Generation for Hybrid Systems Using Clustering and Learning Techniques. 589-590 - Pallavi Das, Jitendra Yadav, Sujay Deb
Mixed Mode Simulation and Verification of SSCG PLL through Real Value Modeling. 591-592 - Jais Abraham, Shankar Umapathi, Sumitha Krishnamurthi:
Test Time Minimisation in Scan Compression Designs Using Dynamic Channel Allocation. 593-594 - Bapi Kar
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. 595-596 - Debiprasanna Sahoo
MSimDRAM: Formal Model Driven Development of a DRAM Simulator. 597-598 - Rahul Shrestha, Utkarsh Rastogiy:
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier. 599-600 - Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan:
RHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels. 601-602 - Tomoya Akabe
Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays. 603-604
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