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IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 72
Volume 72, Number 1, January 2025
- Surachoke Thanapitak
, Prajuab Pawarangkoon
A 38.4 nW, 1.2 V, 250-Hz, 2nd-Order gm - C LPF With Degenerative SCP Transconductors Achieving 800-mVPP Input Range and 82.1- μVrms IRN for ECG Acquisition. 3-7 - Heungsik Eum
A Sub-1-V Capacitively-Biased Voltage Reference With an Auto-Zeroed Buffer and a TC of 18-ppm/°C. 8-12 - Yani Li
A Low Quiescent Current Fast Transient LDO Regulator With Segmented Pass Transistors. 13-17 - Ahmed S. Elwakil
Closed-Form Expressions for the Input Impedance of Some 2-D Fractal Circuit Networks. 18-22 - Han Yang
A 275 μ W 81.5 dB-SNDR and 200 kS/s CT IDSM With an AC-OSA-Based Integrator Using CNRS and FIR DACs. 23-27 - Chao-Yen Hsu
A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers. 28-32 - Karolos-Alexandros Tsakalos
Experimental Evaluation of Silicon Nitride Memristors as Coupling Elements for Chimera States in Chaotic Oscillator Networks. 33-37 - Mookyoung Yoo
Zero-Drift Fully Differential Amplifier With Ping-Pong Auto-Zero Stabilization and Digitally-Assisted Coarse Automatic Offset Calibration. 38-42 - Geonwoo Park
A Frequency Synthesizer With Automatic Frequency Calibration Robust to Initial Phase Error and Phase-Noise Enhanced Ring Oscillator. 43-47 - Zhifei Lu
A Novel NN-Based Fast-Convergence Background Calibration for Timing Mismatch in TI ADCs. 48-52 - Hua Chen
A Digital IR-UWB Transmitter With High Spectrum Utilization and AM-PM Distortion Calibration. 53-57 - Ningzheng Sun
A Balanced Power Amplifier With Complementary Adaptive Bias in 28-nm Bulk CMOS for 5G Millimeter-Wave Systems. 58-62 - Ke Chang
MASH ΣΔ Modulator With Filter Mismatch Shaping Technique. 63-67 - Liyan Feng
A 6-64-Gb/s 0.41-pJ/Bit Reference-Less PAM4 CDR Using a Frequency-Detection-Gain-Enhanced PFD Achieving 19.8-Gb/s/μs Acquisition Speed. 68-72 - Yu-Chi Yen, Shen-Iuan Liu
A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration. 73-77 - Honggu Kim
All Stochastic-Spiking Neural Network (AS-SNN): Noise Induced Spike Pulse Generator for Input and Output Neurons With Resistive Synaptic Array. 78-82 - Shichao Jin
A Temperature-Compensated Ku-Band Four-Beam Phased-Array Receiver With Low Attenuation and Relative Phase Variations. 83-87 - Dongwei Pang
An X-Band 7-Bit High Resolution and Ultra-Low Amplitude Variations Phase Shifter With Current Correction Technique. 88-92 - Linwei Wang
A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer. 93-97 - Changchun Zhou
A 200-MS/s 12-b Cryo-CMOS CS DAC for Quantum Computing. 98-102 - Seongchan Bae
A 600-V Peak-to-Peak 65-dBc RF Signal Source for Trapped-Ion Quantum Computing. 103-107 - Marie Andrä
UFERI - Ultra-Fast Energy Resolved Imager for Next Generation Synchrotron Experiments. 108-112 - Lijuan Wang
A 220-GHz LNA With 9.7-dB Noise Figure and 24.6-dB Gain in 40-nm Bulk CMOS. 113-117 - Dongin Min, Changkun Park
Ka-Band CMOS Variable-Gain Amplifier Using Capacitive Compensation Technique to Suppress Phase Error. 118-122 - Mehran Ghahramani
A Bandwidth Extension Technique for Improving Jitter in Ring-VCO-Based Sub-Sampling PLLs. 123-127 - Jiaxu Cong
SRRT: An Ultra-Low-Power Unidirectional Single-Wire Inter-Chip Communication for IoT. 128-132 - Juwon Kim
A Compact Ka-Band Variable Gain Phase Shifter With Bi-Directional Phase Inverting Amplifier. 133-137 - Hongjie Zeng
Parasitic-Aware Analysis and Design of a Wideband gm-Boost Low Noise Amplifier at K-Band. 138-142 - Hyogyoung An
An Area-Efficient CMOS Cross-Coupled LC-VCO Using Nested Intertwined Tail Inductors. 143-147 - Yuye Yang
An On-Chip AC Coupled AFE With Asymmetric Output Stage for d-ToF LiDAR. 148-152 - In Cheol Yoo
A 120 GHz gm-boosting Low-Noise Amplifier in 40-nm CMOS. 153-157 - Jian Zhang
A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology. 158-162 - Luhua Lin
A 7.5-GHz Frequency-Hopping CDMA UWB Transceiver for Secure Multi-Sensor Connectivity. 163-167 - Insu Han
A Dual Power Mode Q/V-Band SiGe HBT Cascode Power Amplifier With a Novel Reconfigurable Four-Way Wilkinson Power Combiner Balun. 168-172 - Zhongzhen Tong
In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET. 173-177 - Shixing Li
A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications. 178-182 - Hong-Jian Huang, Chuan-Ke Zhang
Stability Analysis of Amplidyne Electrical Systems With Time-Varying Delay via a Matrix-Injection Method. 183-187 - Lingling Wu
Conservation of Total-Activity-Degree for Mix-Valued Logical Networks. 188-192 - Hanguang Su
ADP-Based Self-Triggered Optimal Control of Active Loads in DC Microgrid. 193-197 - Kang-Li Xu
Parametric Interpolation Model Order Reduction on Grassmann Manifolds by Parallelization. 198-202 - Xiaoyan Diao, Jun Xia
Continuous Practical Terminal Sliding Mode Controller for Boost Converters: Design and Experimental Evaluation. 203-207 - Zhongyang Wang
Optimal Output-Feedback Controller Design Using Adaptive Dynamic Programming: A Permanent Magnet Synchronous Motor Application. 208-212 - Jiemei Zhao
Reachable Set Estimation of Inertial Complex-Valued Memristive Neural Networks. 213-217 - Yongxiao Tian
Time-Elapsed-Reliant Observer-Based Control of Semi-Markov Jump Linear Systems With Bilaterally Bounded Sojourn Time. 218-222 - Fan Liu
Dynamic Self-Triggered Adaptive Control for Voltage Regulation of DC Microgrids. 223-227 - Shunwei Hu
H∞Optimal Load Frequency Control of Power System: A Novel Model-Free Approach. 228-232 - Zhijian Hu
Resilient Frequency Estimation for Renewable Power Generation Against Phasor Measurement Unit and Communication Link Failures. 233-237 - Jing Xie
H∞ Anti-Disturbance Bumpless Transfer Control for Switched Affine Systems With Its Application to a Circuit Model. 238-242 - Jianfei Wang
A Compact and Efficient Hardware Accelerator for RNS-CKKS En/Decoding and En/Decryption. 243-247 - Jianfei Wang
An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. 248-252 - Yazheng Tu
LTE: Lightweight and Timing-Efficient Unequal-Sized Polynomial Multiplication Accelerators. 253-257 - Wenyue Zhang
Min-Pooling Cost Aggregation for Semi-Global Matching of Stereo Vision Processor. 258-262 - Khalid Javeed
Efficient Number Theoretic Transform Architecture for CRYSTALS-Kyber. 263-267 - Guosheng Zhang
Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable System. 268-272 - Jialiang Zhu
A 28 nm 75.6 KOPS 13 nJ Computing-in-Memory Pipeline Number Theoretic Transform Accelerator for PQC. 273-277 - Khai-Duy Nguyen
ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications. 278-282 - Akash Dev Roshan
Hardware-Optimized Regression Tree-Based Sigmoid and Tanh Functions for Machine Learning Applications. 283-287 - Haonan Zhang
An Efficient Brain-Inspired Accelerator Using a High-Accuracy Conversion Algorithm for Spiking Deformable CNN. 288-292 - Zhengqing Zhong
MorphBungee-Lite: An Edge Neuromorphic Architecture With Balanced Cross-Core Workloads Based on Layer-Wise Event-Batch Learning/Inference. 293-297 - Dalibor Biolek, Zdenek Biolek, Zdenek Kolka, Viera Biolková, Zdenek Kohl:
Modeling and Emulation of Extended Memristors: Two-Port Approach Revisited. 298-302 - Liting Li
A Soft-Switched Semi Dual Active Half Bridge Converter With Voltage Match Trapezoidal Modulation Control. 303-307 - Weidong Xue
A 24V-to-1V Triple Series-Capacitor Buck Converter With Low-Voltage Power Switches. 308-312 - Guangyao Li
An Integrated Mutually Compensatory Dual Receiver for AGV Misalignment-Tolerant IPT Charging. 313-317 - Xiangwen Xin
A 96-nA Quiescent Current LDO With Embedded BGR Using Adaptive Pole Tracking and Adaptive Transconductance Technique. 318-322 - Guangyu Yan
A Simultaneous Wireless Power and Full-Duplex Data Transfer System Using a Mix of Inductive and Capacitive Couplings. 323-327 - Zhong Zhao
A Peak-Valley Current-Mode Buck Converter With 3% to 95% Duty Cycle. 328-332 - Chaolai Da
Pulse Synchronization Scheme for Undersea BWPT System Based on Simultaneous Wireless Power and Data Transfer Technology. 333-337 - Chan-Ho Lee
A 12-V Input 0.3 V-to-0.6 V Output Imbalanced Inductor-Currents Converter That Achieves a Peak Efficiency of 90.7%. 338-342 - Ali Alshawabkeh, Georgios Tzounas
Instantaneous Frequency Estimation in Unbalanced Systems Using Affine Differential Geometry. 343-347 - Mengxia He
Source Number Estimation in 2D Uniform Circular and L-Shaped Arrays With Unknown Nonuniform Noise. 348-352 - Zongxiang Wang
Erratum to "A 1-27 GHz SiGe Low Noise Amplifier With 27-dB Peak Gain and 2.85±1. 45 dB NF". 353
Volume 72, Number 2, February 2025
- Nannan Li
A 10-Bit 500-MS/s Pipelined SAR ADC With Nonlinearity-Compensated Open-Loop Amplifier and Parallel Conversion Through Comparator Reusing. 354-358 - Yuqing Lou, Hanbo Zhang, Jun Li
A 10.23-Bit ENOB 1 kS/s Differential VCO-Based ADC With Resistive Input Stage in Low-Temperature Poly-Silicon TFT Technology. 359-363 - Yifu Guo
A 16-Bit 1.6-kS/s ΔΣ Modulator Based on Folded-Cascode Dynamic Amplifier With Speed Enhancement and PVT-Tracking Techniques. 364-368 - Taehwan Kim
A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM. 369-373 - Sihao Chen
A 28-nm 8-Bit 16-GS/ DAC With >60 dBc/>40 dBc SFDR Up To 2.3 GHz/5.4 GHz Using 4-Channel NRZ-Output-Overlapped Time-Interleaving. 374-378 - Sizhen Li
A 140 pW, -77 dB PSRR, PMOS-Only Voltage Reference Using Pre-Regulation Technique With Gate and Bulk Feedback. 379-383 - Kwok Cheong Li
A Flying-Capacitor-Based Reset Scheme for Low Power Dynamic Comparator. 384-388 - Xiangxun Zhan
A Series-LC-Assisted Oscillator Achieving -140.2 dBc/Hz Phase Noise and 187.5 dBc/Hz FoM at 10 MHz Offset From 10.7 GHz. 389-393 - Safaa A. Abdelfattah
Instrumentation Amplifier Input Impedance Calibration With Machine Learning-Based Optimizations. 394-398 - Jong-Won Park
A Broadband Gm-Boosted Active Feedback CMOS Low-Noise Amplifier for Low- and Mid-Band 5G Applications. 399-403 - Tao Zhang
A Wideband Compact Digitally-Assisted Variable Gain Phase Shifter for Ka-Band Applications. 404-408 - Ayyappadas Rajagopal
A Real-Time Hardware-in-the-Loop System Incorporating Software Defined Radios for Emulating Multi-Sensor Networked Control Systems. 409-413 - Haiyang Cao
Enhanced Position Estimation Accuracy Based on Improved Super-Twisting Observer and Position Compensation PLL for PMSM Sensorless Control. 414-418 - Minkyu Ko
A Low-Power Fully-Static Contention-Free Flip-Flop With Reduced Clock Load. 419-423 - Kye-Seok Yoon
Extended ZVS Range via LC Resonance in Current-Fed Parallel Resonant Converter for AGV Wireless Power Transfer. 424-428 - Wei Yu, Dongyuan Lin
Extended H∞ Filtering in RKHS for Nonlinear Systems With Uncertainty. 429-433
Volume 72, Number 3, March 2025
- Debajit Basak
On the Effect of Memory Error in a Time-Interleaved Pipeline ADC With a Shared Residue Amplifier. 434-438 - Tailong Xu
Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. 439-443 - Xufeng Liao
An 85.5% PCE and 99.31% TE Piezoelectric Energy Harvesting Interface With Sub-One-Cycle Sampling and Dual-Loop MPPT. 444-448 - Jiajun Tang
A 12.6-pJ/Conversion Temperature Sensor With 0.98-mV/K Temperature-Voltage Sensitivity. 449-453 - Tiancheng Zhao
Unraveling Negative Feedback Translations: Gains, Peaking, Stability, and Loop Variations. 454-458 - Dan Shi
A 0.35-0.5-V 0.0136-mm² 12 -MHz Digital Frequency-Locked Loop With 1.06%/V Line Sensitivity in 65-nm CMOS. 459-463 - Haoyu Zhuang
A High-Accuracy Bandgap Reference With Compact Output Driver. 464-468 - Junfan Yan
A 0.2-3 GHz Inductor-Less LNA Using Noise-Canceling and Dual-Resistor Feedback Technique. 469-473 - Dong-Seob Shin
A 1.62 - 10-Gb/s CDR Using Wide-Range VCO With Linearized KVCO. 474-478 - Eslam Elmitwalli
Constraint-Aware Annealing for CMOS-Based Ising Machine LDPC Decoder. 479-483 - Hadi Hayati
A 400-Mbps 1.05 pJ/Bit IR-UWB Transmitter for High-Density Neural Recording Systems. 484-488 - Wenjie Mei
Learning and Current Prediction of PMSM Drive via Differential Neural Networks. 489-493 - Xiang Wang
Predefined-Time Command Filtered Control for Tracking and Synchronization of Multi-Motor Servo Systems With Fuzzy Approximator. 494-498 - Bing Zhang
Inverse-Free Hybrid Spatial-Temporal Derivative Neural Network for Time-Varying Matrix Moore-Penrose Inverse and Its Circuit Schematic. 499-503 - Dejun Xu
A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber. 504-508 - Guanyu Chen, Mingju Chen
An Edge Neuromorphic Processor With High-Accuracy On-Chip Aggregate-Label Learning. 509-513 - Mookyoung Yoo
DRAM Physically Unclonable Function (PUF) Using Dual Word-Line Activated Twin-Cells. 514-518 - Mingliang Ding
Security Control for Networked Nonhomogeneous Stochastic Switching Power Systems With DoS Attacks. 519-523
Volume 72, Number 4, April 2025
- Shuqun Ding
A 74.3 dB SNDR 3rd-Order VCO-Based DSM With Built-In Passive Low-Pass Filter in 65 nm CMOS. 524-528 - Yiyun Mao
An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System. 529-533 - Yongshan Wang
An All-Digital and Wide-Range De-Skew Circuit With Dual-Edge Correction Scheme for Source Synchronous Interfaces. 534-538 - Junyuan Tu
A 140-GHz CMOS Four-Way Power Combining Doherty Power Amplifier With Adaptive Biasing. 539-543 - Yuhua Liang
An 8-to-12-Bit Resolution-Reconfigurable SAR ADC With Fast-Window-Switching Technique. 544-548 - Yuting Chen
A Compact RF Module With Hybrid Stacked Transformer and Integrated Transceiver Switch in 65 nm CMOS Technology. 549-553 - Taegun Yim
Single-Ended Back-Bias Voltage Generator Using One Pumping Capacitor. 554-558 - Ricardo Riaza
A General Form for the Extra Element Theorem. 559-563 - Venakata Sitaraman Puram
Comments on "Dual-Band Branch-Line Couplers With Short/Open-Ended Stubs". 564-567 - Junhyeop Kim
Cryogenic CMOS Active Mixer Employing Transformer-Based Current-Bleeding Technique. 568-572 - Saurabh Pandey
Sampled Wiener Time Delay System Identification. 573-577 - Liyuan Yang
Adaptive Dynamic Surface Control With Disturbance Observer for Oxygen-Excess Ratio of Proton Exchange Membrane Fuel Cell Systems. 578-582 - Tianbo Zhang, Keyou You
Distributed Closed-Loop Reference Adaptive Learning Control for Parallel Mutual Inductance Circuits. 583-587 - Jiaping Qiang, Li Li
Practical Prescribed-Time Tracking Control for High-Order Nonholonomic Systems With Matched and Mismatched Uncertainties. 588-592 - Yang Gu
Dynamic Event-Triggered-Based Iterative Filtering and Fault Compensation for PMSG-Based Wind Turbine Systems Under Deception Attack. 593-597 - Yongqian Wang, Zhenghao Ni
Asynchronous Reduced-Order Filtering for Markov Jump Systems and its Application in PWM Circuits. 598-602 - Zohaib Tariq, Haroon Waris
Low-Cost Yet Effective Trojan Mitigation Techniques for Approximate Systems. 603-607 - Yang Zhou, Yang Wang, Wenxin Yin, Yazheng Jiang, Jingchuan Wei, Yubin Qin
BeaCIM: A Digital Compute-in-Memory DNN Processor With Bi-Directional Exponent Alignment for FP8 Training. 608-612 - Xin-Yu Shih
Design and Hardware Implementation of Low-Latency 4-Splitting Tree-Structure-Based K-Means Clustering Trainer and Classifier Chip for Detecting Cybersecurity Attacks. 613-617 - Haibiao Zuo
A 1.46-pJ/bit, 149-KF² RO TRNG Based on Reference-RO-Free Thresholding of Jitter Accumulation. 618-622 - Juntao Guan
PIMSR: An Energy-Efficient Processing-in-Memory Accelerator for 60 FPS 4K Super-Resolution. 623-627 - Xiudeng Wang
A Power Self-Sufficient Managed Energy Harvester With Dual-Source Synergistic Cold-Start Capability. 628-632 - Jianhang Zhou, Jing Yan
Consensus Estimation of Flow Field via Underwater Sensor Networks in Inhomogeneous Medium. 633-637
Volume 72, Number 5, May 2025
- Mahesh Kumar Chaubey
A 43.4-dB Gain 7.6-mW 197.5% Bandwidth Double Noise-Canceling Cryogenic LNA Using Gain Peaking Technique for Multiple Spin Qubit Readout. 638-642 - Surachoke Thanapitak
A Nanopower Folded-Cascode EEG Lowpass Filter. 643-647 - Yifan Li
A 1-Mbps 0.7-nJ/Bit Low-Complexity High-Robust FM-UWB Transmitter Under a Sub-1-V Supply. 648-652 - Jiang Luo
A 10 to 15 GHz Digital Step Attenuator With Robust Temperature Tolerance Across -55 ∘C to 125 ∘C. 653-657 - Jiangbo Chen
A V-Band FMCW Signal Generator With Hybrid Dual-Path VCO Technique Achieving 13.6-GHz Chirp Bandwidth. 658-662 - Bhawna Tiwari
Multi-Bit Capacitance Sensing System Using a-IGZO TFT Technology for Smart Wearables. 663-667 - Abdul Qahir
High-Power 270-GHz Oscillator With Harmonic Output Power Optimization Using Series Resonance Feedback. 668-672 - Tian Tian
A 357-706-MHz Low-Pass Filter With Oscillator Mode for Bandwidth Calibration. 673-677 - Qingjiang Xia
An Energy-Efficient Capacitance-to-Digital Converter With Top and Bottom Plate Sampling for Pressure Sensors. 678-682 - Bibhudutta Satapathy
An Adaptive Body Tuned Sense Amplifier for Energy Efficient In-Memory Computing. 683-687 - Rui Luo
A Single-XO Dual-Output Frequency Reference Featuring Adaptive RTC Calibration Achieving 0.63 ppm/°C Temperature Coefficient From -40 °C to 125 °C. 688-692 - Ya Zhao
A 0.0019-mm² LC-Ring Oscillator With an Ultra-Compact Transformer Achieving 175.2 dBc/Hz FoM@1MHz and 202.4 dBc/Hz FoMA. 693-697 - Yigi Kwon
A 10-Bit 500-MS/s Pipelined SAR ADC With Feedback Factor Compensation in 6-nm FinFET. 698-702 - Xing Wang
First-In-Last-Out Data Weighted Averaging Technique for Multi-Bit ΔΣ ADCs. 703-707 - Yun Qian
A D-Band Low-Noise Amplifier With Gm-Boosting Technique Based on Asymmetric Coupling. 708-712 - Shuang Liu
Highly-Efficient Broadband GaAs HBT Doherty Power Amplifier With Harmonic Control Technique for 5G Application. 713-717 - Zhuming Li
A 59.2-83.3 GHz CMOS LNA With 18.1 dB Gain and 5.1 dB NF Using Gate-Drain Transformer. 718-722 - Youming Zhang
A 4 × 4 Fully Integrated RF Transceiver in 6 GHz Frequency Band With Single-Channel Bandwidth of 400 MHz and PHY Data-Rate of 8.8 Gbps. 723-727 - Boyang Zhang
A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS. 728-732 - Suraj Dudhe
A Portable Meconium Aspirator With Fractional Augmented Pressure Control System. 733-737 - Haiyang Cao
Fixed-Time Adaptive Extended State Observer-Based Enhanced ADRC for Electric Motor Drives. 738-742 - Kejie Wang
Cooperative Resilient Secondary Control for AC/DC Microgrid Under Cyber Attacks. 743-747 - Tianxiang Dong, Yiwen Qi
Efficient Self-Learning Tracking Control for Switched Systems: A Triggered-Learning Model Predictive Control Method. 748-752 - Kangning Wang
ITP-PAD: A Timing Monitoring Mechanism for AVS Systems Using Intersection Timing Prediction and Path Activation Detection. 753-757 - Pan Zhao
HEAT: Efficient Vision Transformer Accelerator With Hybrid-Precision Quantization. 758-762 - Mahipal Dargupally
Robust and Reliable Energy-Efficient Level Shifter. 763-767 - Longning Qi
Energy Efficient On-Chip Memory for Next Generation MCU. 768-772 - Jaehwan Kim
Offset-Tolerant Body-Biased Sense Amplifier With Rise-Time Control Technique for SRAM. 773-777 - Chenhao Li
A Depletion-Mode GaN-Based Envelope Tracking Supply Modulator Utilizing a Novel Coupled PWM Generator. 778-782 - Kuan Deng
An Area-Efficient High-Precision Analog Front End for Battery Management System. 783-787 - Md Sartaj Ahmed
A Reduced Capacitance H-9 Five-Level Switched Boost Capacitor Transformerless Inverter. 788-792 - Francesco Gabriele
A Novel Bypass Architecture for RB-COT Buck Converters. 793-797 - Xu Ren
A Current-Mode Multiply-Accumulate Macro in Sensing-Computing Fusion System for Feature Extraction and Redundancy Reduction. 798-802 - Fei Tan
A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm. 803-807
Volume 72, Number 7, July 2025
- Yuhua Liang
A Peak-Injection CLS Technique for PVT-Robust Switched-Capacitor Amplifier. 873-877 - Jingjing Liu
An 88.96 dB HDR CMOS Image Sensor Modeled on Visual Neuronal Response. 878-882 - Victor R. Gonzalez-Diaz
On-Chip Active Filter for Electrocardiographic Signals Through CMOS Pseudo Resistors. 883-887 - Jongchan An
A 1.58 pJ/b 9 G bps Reference-Less Clock and Data Recovery Circuit With Sigma Range Detector. 888-892 - Zhuoheng Xie, Yue Feng, Bo Huang, Zihan Zhang, Heng Zhao, Lan Liu, Zhihao Liu, Zhigang Li
A Ku-Band Broadband 8-Channel 8-Beam Phased-Array Receiver With Polarization Agility and Beam Reconfiguration for SATCOM Applications. 893-897 - Yuqin Dou
A Novel Error Metric for Evaluating the Error Correction Capability of Approximate Units. 898-902 - Yuxin Jiang
Reachable Set Estimation of Memristive Inertial Neural Networks. 903-907 - Wenxiao Cai
OscNet: Machine Learning on CMOS Oscillator Networks. 908-912 - Bowei Zhang
Resilient Optimal Virtual Synchronous Generator Control Under DoS Attacks. 913-917 - You Wang
A Dual-Swing-Sample-and-Couple Sense Amplifier With Large Sensing Margin for STT-MRAM. 918-922 - Kyle Mooney
Low-Cost Low-Power Failure-Tunable Memory for Differential Privacy. 923-927 - Yi Wei
NeuCore: A Novel Neuromorphic Processor Architecture With On-Chip Event-Driven Learning. 928-932 - Muxuan Gao
OnSort: An O(n) Comparison-Free Sorter for Large-Scale Dataset With Parallel Prefetching and Sparse-Aware Mechanism. 933-937 - Luca Tegazzini
High-Precision MUX-Based Digital Delay Interpolators Based on a Novel Transistor Sizing Algorithm. 938-942 - Mingju Chen
A Visual-Cortex-Mimetic Tiny Neuromorphic Vision Processor Based on Reconfigurable Cortical Neuron Unit. 943-947 - Zekun Zhang
A 1998-Mpixels/s 75-pJ/pixel Slice-Alternated Display Stream Compression Encoder. 948-952 - Yao Li
A 0.071pJ/Bit Flexible Multi-Mode Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF. 953-957 - Kalle I. Palomäki
Memory Optimized, High Signal Quality Direct Digital Frequency Synthesizer on an FPGA. 958-962 - Divyanshu Divyanshu
Hardware Aware Polyalphabetic Cipher Design Using Spin-Orbit Torque Controlled Spintronic Devices. 963-967 - Mykola Lukianov
Scalable Multiport DC-DC Converter for Bidirectional EV Charging in DC Traction Grids. 968-972 - Tao Li
A Novel Reconfigurable Wireless Charging System Achieving Constant Current and Constant Voltage Conversion by a Single Secondary-Side Switch. 973-977
Volume 72, Number 8, August 2025
- Richard Barrie, Ming Yang
An FPGA-Accelerated Platform for Post-FEC BER Analysis of 200 Gb/s Wireline Systems. 978-982 - Karsten Bergthold, Hagar Hendy, Elaine Greenfield
Enabling Long Chain Lengths and High-Throughput for Time-Domain Neuromorphic Computing. 983-987 - Faraz Adin
98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR. 988-992 - Somayeh Davar
Enhanced U-Net Architecture for Brain Tumor Localization and Segmentation in T1-Weighted MRI. 993-997 - Kai Li
A 28.4-to-39.2 GHz Low-Power Injection-Locked Frequency Quadrupler With Reconfigurable Pre-Filter-Amplifier. 998-1002 - Piotr Kmon
SPECTRUM1k - 75 μm Pixels Pitch IC With In-Pixel Histogramming for X-Ray Color Imaging. 1003-1007 - Yutao Peng
A Neural Network-Enhanced Digital Background Calibration Algorithm for Residue Amplifier Nonlinearity in Pipelined ADCs. 1008-1012 - Jialei Wu
Discharge Correction Under Asymmetric Electrode-Electrolyte Interfaces in Bipolar Stimulation. 1013-1017 - Andrea Fasolino
Calibration-Free Edge-Computing IMC Macro With Direct Current-to-Digital Conversion. 1018-1022 - An Sun
A 0.2-19GHz Zero-IF Reconfigurable Quadrature Transmitter With T-Coil Matching Network. 1023-1027 - Liang-Chen Tsai
A 28-GHz CMOS Power Amplifier With Adaptive Bias and Phase Compensation for Gain and Phase Linearity Enhancement. 1028-1032 - Jierui Chen, Chuang Yang
Parallel and Pipelined BRAM-Based Matrix Transposition for 6G. 1033-1037 - Qiankang Hou
Improved Disturbance Rejection and Noise Suppression Properties for PMSM Speed Control Systems Using Different Order Fast Finite-Time Extended State Observers. 1038-1042 - Cong Huang
An Encoding-Decoding-Based State Estimation Scheme for State-Saturated Systems Under Buffer-Aided Mechanism. 1043-1047 - Yi Lu
Hybrid Scheduling-Based Asynchronous H∞ Control for Markov Jump Power Systems With Cyber Attacks. 1048-1052 - Jiaoni Wang, Jiayue Sun
Privacy-Preserving Optimal Battery Control for Energy Storage Systems Using Adaptive Dynamic Programming. 1053-1057 - Ya Gu
The Three-Stage Identification Method of the Sandwich Model With Hysteresis. 1058-1062 - Jianbing Feng
A Benders-Combined Safe Reinforcement Learning Framework for Risk-Averse Dispatch Considering Frequency Security Constraints. 1063-1067 - Qiang He
A Cost and Speed Co-Optimized Parallel Stochastic Multiplier for Binary Inputs Supporting Variable Bit-Widths. 1068-1072 - Yang Zhang, Xilong Kang, Weixuan Wang, Yizhi Ding, Lizheng Ren, Yiran Zhang, Ruiqi Tan, Zhen Wang, Hao Cai, Bo Liu:
KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM. 1073-1077 - Xiaofeng Huang
Efficient Hardware Architecture Design of K-Means Clustering Algorithm for AV1 Palette Mode Coding. 1078-1082 - Fanny Spagnolo
HIMAM: Hardware Implementation of Multiply-and-Max/Min Layers for Energy-Efficient DNN Inference. 1083-1087 - Tao Zhang
UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination. 1088-1092 - Zhan Zheyu, Hainan Liu, Duoli Li, Ma Quangang, Wenxin Zhao, Zhenzhen Yan
Single-Event Upset Monitor-Based Radiation-Hardened Latch for Multi-Node Upset. 1093-1097 - Minglong Jia
Body-Biased Hybrid Sense Amplifier With High Offset Tolerance for Low-Voltage SRAMs. 1098-1102 - Yi Chen Lee
A Switch-as-Resistor Self-Adaptive Gate-Biasing Technique for Optimized Forward and Reverse Conduction in a CMOS Rectifier. 1103-1107 - Won-Gyu Kim
A 1.8-5.5-V LDO-BGR System With LACM Buffer for High PSRR in Camera Applications. 1108-1112 - Tianqi Li
Small-Signal Modeling of an S-S Compensated IPT System Under Frequency Modulation. 1113-1117 - Zhenhao Li, Wenhai Qi
Bumpless Transfer Control for Discrete Semi-Markov Switching Power System With Cyber Attack. 1118-1122 - Yanyun Pu
Mamba-Unet-Depth: Enhancing Long-Range Dependency for Photon-Efficient Imaging. 1123-1127
Volume 72, Number 9, September 2025
- Zhihao Zhang
A Switchable Sub-3GHz/Sub-6GHz LNA With 0.4-1.1dB NF Using Triple-Feedback and Tunable Inter-Stage Matching Strategies. 1128-1132 - Simon Ooghe
A Bit-Level Double Counter Enabling Power-Efficient High-Bandwidth VCO-ADCs. 1133-1137 - Xiao Wang
A 2-MHz BW 64.5-dB SNDR 0.45-1.05 GHz Direct IF/RF Digitization Subsampling Bandpass DSM Utilizing a Capacitive-Stacking N-Path Filter. 1138-1142 - Suiyang Liu, Zhongjie Guo
A High-Speed Dual Feedback Loop Column Buffer for Ultra Large Pixel Array CMOS Image Sensors. 1143-1147 - Shaogang Wang
A 26.5-29.5 GHz Doherty Phased-Array Transceiver Front-End With 7-Bit Phase Shifter and 16% Back-Off Drain Efficiency. 1148-1152 - Jianhang Yang
An 8.1 dB SNRMIN, 17.8 pJ/Conv-Step, Code-Domain Noise Suppression Baseband Scheme for Ultra-Low-Power Receiver. 1153-1157 - Ali Rezapour
A Swing- and Gain-Enhanced Mirrored Dynamic Amplifier. 1158-1162 - Xiaofei Liao, Dixian Zhao
A 3.9-8.2-GHz Wideband Frequency Synthesizer With an Inductive Multiplexing Output Network for SATCOM Applications. 1163-1167 - Chun-Tse Su
A Calibration-Free 12-Bit 1.5-GS/s Pipelined ADC With Merged Sub-ADC Quantization Technique. 1168-1172 - Nan Jiang
An Ultra-Low-Power Time-Domain Level-Crossing ADC With Adaptive Sampling Rate. 1173-1177 - Peng Gu
A Ka-Band Fully Integrated CMOS 1T3R Transceiver for Monopulse Radar Applications. 1178-1182 - Zonglin Ye
A 6.8-14.4GHz Calibration-Free Fractional-N RO-Based Harmonic-Mixing Frequency Synthesizer Achieving -80.7dBc Fractional Spur. 1183-1187 - Mohammad Reza Nikbakhsh
On the Impact of Idle-Time Reduction on FMCW Radar Phase Noise Performance. 1188-1192 - Jihee Kim
A 2.5-48 Gb/s 16.6 ns Turn-On Time NRZ/PAM4 Pulse-Based Rapid-On/Off Baud-Rate CDR for Mobile Interfaces. 1193-1197 - Seunghoon Lee
An I/Q Imbalance Calibration Scheme for 5G Direct-Conversion Transmitter. 1198-1202 - Shiwei Wu
An Ultra-Compact Ka-Band Folded Phased-Array Transceiver Front-End With Bidirectional 20-dB Gain Control. 1203-1207 - Kyoungseok Song, Donggun Lee, Geunhaeng Lee
A 2.54 Gbps, 1.22 pJ/Bit, IR-UWB Transmitter With a Power-Gating Technique. 1208-1212 - Joonseok Park
Design of Compact Size CMOS VCO Using Dual-Primary Transformer With Dual-Core for Wide Tuning-Range. 1213-1217 - Michel W. de S. Campos
Development of a Hybrid Fractional-Order Fuzzy-PID Controller Applied to a DC-DC Buck Converter. 1218-1222 - Ruonan Lu
Contrastive Learning-Based Dual Autoencoder for Anomaly Detection in Loader Gearboxes. 1223-1227 - Yao Xu
Data-Driven Near-Optimal Reduced Tracking Control of SPSs With Application to PMSM. 1228-1232 - Qifan Wang
A Novel Voltage-Sensorless Grid Voltage Full Feedforward Estimator-Based Current Control Strategy for a Grid-Connected Inverter. 1233-1237 - Qing Yang
Learning-Based Scaling Scheme for Markov Jump Systems and Its Application in Operational Amplifier Circuit. 1238-1242 - Jiawei Xie
A Compact Dual-Channel WPT System Based on Decoupled Integrated Coils for Power Enhancement. 1243-1247 - Qiliang Zhang
Self-Triggered Delay Output Regulation for Boolean Control Networks. 1248-1252 - Yujun Xie
Area-Efficient Modular Multiplication on FPGA. 1253-1257 - Lichen Feng
A 36 mJ/Inf Convolution Accelerator With Reduced Memory Access and Regrouped Sparse Kernels for Environment Sound Classification on Edge Devices. 1258-1262 - Baoying Yu
ZRHDC: A Lightweight HDC Architecture With Zero ROM Overhead. 1263-1267 - Hyojeong Choi
Chaotic Nature of Integer Sequences From Primitive Linear Feedback Shift Registers. 1268-1272 - Jinhoon Jo, Jueun Jung
An Energy-Efficient Image Deblurring Accelerator With Quad-Base-Quad-Scale Quantized Format and Layer Normalization-Aware Optimization. 1273-1277 - Jialei Sun
An Energy-Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2. 1278-1282 - Haiqiu Huang
A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms. 1283-1287 - Haikuo Shao
An Efficient Layer Normalization Training Module With Dynamic Quantization for Transformers. 1288-1292 - Jaeil Lim
A New Two-Tiered ECC Configuration Method for Cluster Error Correction in HBM Architecture. 1293-1297 - Yuchen Ma
MPN-S: An Algorithm-Hardware Co-Designed Architecture for High-Efficiency Softmax Computation. 1298-1302 - Carlos E. C. Souza
High-Throughput Pseudo-Random Number Generators Over Discrete Chaos. 1303-1307 - Xiao Yang
Bifurcation Analysis of Slow-Scale Oscillation in SIDO Boost PFC Converter Using Time-Frequency Characteristic Representation Method. 1308-1312 - Ning Wang
Automatic Design of Multi-Fold Hyperchaotic System Using Parallel Fractal Algorithm. 1313-1317 - Young-Ju Oh
A 91.7% Peak-Efficiency 48V-to-1V Pseudo Two-Stage Two-Phase Hybrid Buck Converter. 1318-1322 - Ziliang Zhou
A High-Voltage Charge Pump With Pseudo-Continuous Output Regulation Using Dynamic Clock Voltage Scaling. 1323-1327 - Fang Liao, Yanzheng Zhu
Fault Tolerant Control of Switched Affine Systems With Application to Boost Converter: The Transition-Dependent Bumpless Transfer Approach. 1328-1332 - Xuetao Xie
A Fractional Momentum Enhanced Fractional Filter for the Memristor-Based Volume Controller. 1333-1337 - Nadeem Atif
SLICENet: An FPGA-Based Efficient Semantic Segmentation Network for Edge Deployment. 1338-1342
Volume 72, Number 10, October 2025
- Isaac Bruce
Digitally Calibrated Redundancy-Based String DAC: A Novel Architecture for Enhanced Static Linearity. 1343-1347 - Zhiyang Li
A 3.4-GS/s 12-Bit Time-Interleaved Pipelined SAR ADC With Non-Foster Ring Amplifier-Based High-Linearity Track-and-Hold Amplifier. 1348-1352 - Yuguo Xiang
A Low-Power and High-Efficiency Neural Network Based Scheme for Nonlinearity and Memory Effects in Single-Channel ADCs. 1353-1357 - Bram Veraverbeke
A Cryo-CMOS Triple Tail Comparator With Capacitive Over-Neutralization to Suppress Freeze-Out Induced Hysteresis. 1358-1362 - Shengjie Wang
A Low-Power Ka-Band Transceiver With 5.2-GHz Bandwidth for FMCW Radar Applications. 1363-1367 - Long Chen
A Brain-Inspired Intelligent Vision Sensor With Spiking Processing-in-Sensor Architecture for Spike Feature Encoding. 1368-1372 - Jiayu Kuang
A Multi-Channel Direct-Digital-Conversion Front-End Based on Current-Domain Frequency Division Multiplexing. 1373-1377 - Chenggong Wan
A Three-Segment TDC With a Half-Cycle Single-Stage Vernier Ring for SPAD Sensors. 1378-1382 - Yunyou Pu
A Wideband Frequency-Independent IQ Calibration Scheme With 3-GHz-UGB Amplifiers. 1383-1387 - Ahmed Abdelaziz
Adaptation Approaches for PAMN Contingent Decision Equalizers. 1388-1392 - Dongyuan Zhang
Optimal Control of Active Load Interconnected System in DC Microgrid via an Adaptive Decentralized Event-Triggered Mechanism. 1393-1397 - Wei Xie
Multi-Objective H∞/r-Stability Optimal Interval Estimation for Linear Discrete-Time Systems and Application to DC Servo Motor. 1398-1402 - Xinyue Cao
Hierarchical Fusion Estimation With Feedback for Clustered Sensor Networks Subject to Leader and Subordinate Sensors. 1403-1407 - Jiaoyuan Chen
Improved Model-Free Adaptive Load Frequency Control for Multi-Area Power Systems. 1408-1412 - Xiong Yang
Reinforcement Learning for Dynamic Event-Driven Control of Multi-Machine Power Systems. 1413-1417 - Linlin Nie
Hysteresis-Estimator-Based Adaptive Fuzzy Control for Piezoelectric Micro-Positioning Stage With Time-Varying Output Constraints. 1418-1422 - Xiaomin Liu
Task-Oriented Enhanced Self-Learning Speed Synchronization Control of Flexible Coupled Dual-Motor Systems. 1423-1427 - Wenrong Li
Feedback Total-Activity Conservation of Boolean Control Networks. 1428-1432 - Huizheng Wang
BETA: A Bit-Grained Transformer Attention Accelerator With Efficient Early Termination. 1433-1437 - Peng Zhang, Bo Wang, Ning Zhang
An Integrated Configurable FMCW Radar Baseband SoC in 40-nm CMOS. 1438-1442 - Yu Yu
Hardware-Efficient Local-Expansion-Move Accelerator With Confidence-Driven 3D Label Fusion for Real-Time Stereo Vision. 1443-1447 - Pujun Zhou
Timestep-Parallel 4D Neuromorphic Computing Array Enabling High Computing Power Density and High Energy Efficiency. 1448-1452 - Wenzhe Chen
Enhanced Small-Signal Model for Charge-Controlled LLC Resonant Converters Using Time-Domain Analysis. 1453-1457 - Ziying Xie
A State-Switching Digital LDO for PWM Thermo-Optic Tuning in Silicon Photonics. 1458-1462 - Mingrui Zhang
Optimal Control for Power System Signal Processing: A Joint Edge Collaboration and Relay Assistance Framework. 1463-1467 - Oliviero Massi
Gradient-Based Optimization of MEMS Loudspeaker Equivalent Circuit Models via Automatic Differentiation. 1468-1472 - Swagat Bhattacharyya
Performance Bounds for a Maxima-Sampling Envelope Detector. 1473-1477
Volume 72, Number 11, November 2025
- Antonio Liscidini:
Guest Editorial Special Issue on the 2025 ISICAS: A CAS Journal Track Symposium. 1479 - Jun Yang, Jiongyi Du, Zongle Ma, Keping Wang
A BJT-Based Amplifier-Less Temperature Sensor With 12-Bit SAR ADC Readout and ±0.6°C (3σ) Inaccuracy From -40°C to 120°C. 1480-1484 - Rémi Quéheille
A 71% Relative Bandwidth Differential Integrated Power Amplifier With Optimized PAEmax for 5G-NR FR1 Carrier Aggregation Applications. 1485-1489 - Yiming Huang
A DC-35-GHz Switched-Type Attenuator With Second-Order Compensation Technique. 1490-1494 - Xing Liu
An On-Chip Reconfigurable Front-End for Ultra-Low-Power RF Energy Harvesting. 1495-1499 - Zhong Zhang
A Low-Power Partial-Prediction SAR ADC With Feedback Resistor-Assisted Adaptive FIA. 1500-1504 - Jonghyuk Chae
Photon Event Summation and External Readout for Fill Factor Preservation in 32×32 FSI SPAD Array. 1505-1509 - Bingjun Xiong
An Adaptive Dark Current Compensation Analog Front-End With Reconfigurable Transimpedance Amplifier for Fluorescence Temperature Sensors. 1510-1514 - Jahyun Koo
A Fully Differential Distributed RC Oscillator With a Suppression of Noise and Temperature Sensitivities. 1515-1519 - Yanhan Zeng
A 64.7 nA, -65dB@1 kHz, and Dual-Output CMOS Voltage Reference With Multi-Loop Active Load Without Trimming. 1520-1524 - Xiuheng Wu
A 55-nm 10-GS/s 6-b Time-Interleaved SAR ADC With Bandwidth Boosting Techniques. 1525-1529 - Yuan Cao
A 0.787 pJ/bit, 25 Mbps True Random Number Generator Based on Analog Chaotic Tent Map. 1530-1534 - Junmin Park
A 17-fJ/conv-step FoMw and 259-um2 7-Bit C-CIDAC SAR ADC. 1535-1539 - Nidhi Sharma
A Modified Three Stage Dynamic Comparator Achieving Rail-to-Rail Input Common-Mode Range With <86 fJ · ns EDP. 1540-1544 - Zhang Qiu
A Highly-Integrated Wireless Neuromodulation SoC for Compact Injectable Implant. 1545-1549 - Zixiang Liu, Tao Lu
A 7-Bit 1.41-GS/s 2-Bit/Cycle Precharge-Advancing SAR ADC With Fast Discharge Comparator. 1550-1554 - Xiangjian Kong
A Sub-Sampling-Chopper PLL With Residual-Free Charge-Sharing Canceling Achieving 39-fsrms Jitter and -258.2-dB FoMJ. 1555-1559 - Chunxiao Liu
Analysis of Fractional Spurs in a DTC-Assisted ADPLL Exploiting Crystal-Oscillator Waveform With Harmonic-Based Digital Predistortion. 1560-1564 - Yi Chen Lee
A Minimal Loss Gate-Biasing Technique for CMOS Rectifier Achieving 22-dB PDR in GSM900 Ambient RFEH Applications. 1565-1569 - Gichan Yun
A 2.0-mW 70.1-dB SNDR 7.8-MHz BW Continuous-Time Noise-Shaping SAR ADC Using Fully Parallelized Quantization. 1570-1574 - Hiroaki Kitaike
Design and Experimental Verification of 0.9-2.6pW 0.1-0.25V 22nm 2-Bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording. 1575-1579 - Yukun He
A 32 Gb/s Burst-Mode Transimpedance Amplifier With 2.625 ns Reconfiguration Time for All-Optical Network Switching. 1580-1584 - Shuaizhe Ma
A 10-Gb/s 3.6-pA/√ Hz Input Noise Optical Receiver in 28-nm CMOS. 1585-1589 - Hyun-Bin Lee, Won-Young Lee
A 1.62-8.1-Gb/s Single-Loop Referenceless CDR With Fast Frequency Acquisition Technique for Embedded DisplayPort. 1590-1594 - Yuanmiao Lin
An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization. 1595-1599 - Wenyong Zhou
QuadINR: Hardware-Efficient Implicit Neural Representations Through Quadratic Activation. 1600-1604 - Moxiao Lou, Jin Wang
Area-Efficient and Low-Power 8T Compute-SRAM Bitcell Design for Digital Compute-In-Memory Macros in 22nm CMOS. 1605-1609 - Sangmyoung Lee
A 227.1 TOPS/W High Energy-Efficiency PNN-Based 3-D Object Recognition Processor With Spiking Neural Network for Edge Device. 1610-1614 - Yi Yang
BooLUT-CIM: A 52.4 TOPS/W Radix-4 Booth-LUT Digital CIM With Negative-Magnitude-Bits Inversion Storage. 1615-1619 - Weiwei Shi
EEG Motor Imagery Processing System Design and Efficient Hardware Implementation. 1620-1624 - Angelo Garofalo
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. 1625-1629 - Jianfei Wang
PBSAcc: A High-Performance Hardware Accelerator for FHE With Improved Batch Programmable Bootstrapping. 1630-1634 - Yue Shi
An Ultra-Low Quiescent Current Adaptive ZCD Technique for Discontinuous-Conduction-Mode Control Applications. 1635-1639 - Chua-Chin Wang
A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs. 1640-1644 - Yiqing Lan
A Leakage-Suppressing Differential-Drive Rectifier for Sporadic Wearable Triboelectric Energy Harvesting. 1645-1649 - Emmanuel Nti Darko
Ultra-Low Leakage Current Sensor With Large Dynamic Range. 1650-1654 - Dan-Ioan-Dumitru Stoica
A Direct-to-Digital Readout Architecture for CMOS Hall Sensors. 1655-1659 - Anying Jiang
A Novel Bit-Adjustable Column-Parallel ADC for Scalable Emerging Computing Systems. 1660-1664 - Jaeho Lee
A 4-400 K CMOS Voltage and Current Reference With Single-Transistor Noise-Suppression Loop. 1665-1669 - Erxiang Ren
Shuffle-CIM: An All-Analog Computing-in-Memory Macro With Shuffle Scheme and Analog Non-MAC Implementation for Smart Sensing. 1670-1674 - Zuojun Wang
A Millimeter-Wave Frequency Doubler With Wideband Transformer Balun Output Matching and Enhanced Harmonic Suppression. 1675-1679 - Massimo Ghioni
On the Application of the Principle of Energy Equipartition to Linear Time-Invariant RLC Networks. 1680-1684 - Raghav Bansal
A 0.6-V Output, 10-mA Low-Dropout Regulator With Feedback Resistors Shared by an Integrated Single-BJT Voltage Reference. 1685-1689 - Xuzhi Liu
A 7.2-16 GHz 50%-LO Receiver With Enhanced Linearity and High Dynamic Range in 55-nm CMOS. 1690-1694 - Shuang Liu
A 2T1MTJ-Based In-Memory Computing Macro With Time-Domain Accumulation and Ramp-Type Readout. 1695-1699 - Yixi Li
A 0.006-mm2 0.96-LSB-INLPP 8-14-GHz 7b Twin-PI Using an Unequal-Weight Combiner With a Self-Biased-PLL Based Low-Power Compact 4-Phase Clock Generator. 1700-1704 - Ke Chang
SMASH ΣΔM With Leakage Error Suppression. 1705-1709 - Yun-Ta Wu, Shen-Iuan Liu
A Gain-Boosting Reference-Double-Sampling PLL Using Tail-Feedback VCO With Implicit Common-mode Resonance. 1710-1714 - Haochang Zhi
Closed-Loop Pole Analysis via Output Impedance in Miller-Compensated Amplifiers. 1715-1719 - Nimrod Ginzberg
A Voltage-Mode I/Q Switched-Capacitor Doherty Power Amplifier With Dynamic Core Scaling for Enhanced Backoff Efficiency. 1720-1724 - Lingzheng Kong
A D-Band 5-bit SiGe Active Bidirectional Phase Shifter Achieving 0.09-dB RMS Gain Error and 0.86° RMS Phase Error. 1725-1729 - Natachai Terawatsakul
Multimode Cavity Enabling Backscatter Communication for mm-Sized Implants in Freely Moving Animals. 1730-1734 - Zhiguo Yan
Finite-Time Annular Domain H2/H∞ Filtering for Stochastic Markovian Jump Systems and Its Applications in PWM Circuits. 1735-1739 - Wenjie Li
Simplified Hybrid Adaptive Kalman Filter With Fading-Triggered Resonance Mechanism for PMSM Speed-Sensorless Control. 1740-1744 - Yalin Zhang
Distributed Multiconsensus Cooperative Control of Droop-Controlled BESSs Based on Centrality of Eigenvectors. 1745-1749 - Cheng Zhao
A Reconfigurable Digital Compute-in-Memory Architecture With 2:4 Compressed Weight Storage for Highly Sparse Fusion Neural Network. 1750-1754 - Fanny Spagnolo
Design of Energy Efficient RFET-Based Polymorphic Logic Gates. 1755-1759 - Beomseok Kim
An Energy-Efficient 3D Semantic Segmentation Processor With Offset-Wise Weight Quantization. 1760-1764 - Tong Li
Efficient Extraction and Packing Modules for Posit Multipliers. 1765-1769 - Xianrui Dou
Prebond Test of TSV Based on Voltage Skew Amplification. 1770-1774 - L. Hemanth Krishna
Low Complexity Three's Complement Parallel Multiplier Using Special Operators of Ternary Logic. 1775-1779 - Reza Badiei
Low-Power Resource-Efficient FPGA Implementation of Modified FitzHugh-Nagumo Neuron for Spiking Neural Networks. 1780-1784 - Jinrong Zhou, Renlong Li
A SRAM-Based In-Memory Accelerator Featuring Complete SAT Solving and CAM Operations for Efficient Network Transmission. 1785-1789 - Ruoyu Wu
Enhancing Efficiency in Continuous-Time Ising Machine Through Direct Current Comparison. 1790-1794 - Yong Wu, Ziyang Luo
A Reconfigurable Detuned S-LCC Compensated IPT System With Two Discrete Frequencies for Stable Power Against Coupling Variations. 1795-1799 - Yeu-Torng Yau
Hybrid Power Filter for Differential-Mode and Common-Mode Noise Currents. 1800-1804 - Hyunjun Park
A Reconfigurable 3-Level Buck Converter With Supply Voltage Dynamic Split for Loop-Free Rapid VCF-Balancing and Dead-Zone Seamless Transition. 1805-1809 - Wei Yu, Yunfei Zheng
Data-Driven State-of-Charge Estimation for Lithium-Ion Batteries Using Variational Inference. 1810-1814
Volume 72, Number 12, December 2025
- Antonio Liscidini:
Guest Editorial Special Issue on the 2025 IEEE International Symposium on Circuits and Systems. 1816 - Chen Wang
A 13-Bit ENOB Fully Asynchronous Noise-Shaping SAR ADC With Coarse-Fine Comparison, Mismatch Error Shaping and Digital Prediction. 1817-1821 - Javier Granizo
Analysis of Clock Jitter in VCO-ADCs Under Presence of Mismatch and Blocking Signals. 1822-1826 - Kai Jing
A 2.56ppm/°C High-Order Curvature-Compensated Bandgap Reference Utilizing Four-Input Current Feedback Amplifier. 1827-1831 - Ye Wang
A 5.8-GHz 4.8-mW -247.1dB-FoM DTC-Free Sampling ΔΣ Fractional-N PLL With Embedded Phase Interpolation. 1832-1836 - Raghavendra Rukmani Gowrishankar
A Mutually Coupled High Speed Multi-Phase Clock Distribution Scheme for Improved Signal Integrity. 1837-1841 - Purushothaman A
A 31.25 MHz Bandwidth 52.4 dB SNDR VCO-Based ADC With on-Chip Non-Linearity Correction. 1842-1846 - Shanthi Pavan
Noise in Periodically-Switched RLC Networks. 1847-1851 - Marco Tambussi
A Quasi-Passive 78-dB DR 14.9- μW Noise-Shaping SAR A/D Converter for Audio Activity Detection Applications. 1852-1856 - Jacob Dawes, Alyssa Estenson, Louis Marun
Thermal Inkjet Pumping and Flow Rate Estimation for Microfluidics in Lab-on-CMOS Packages. 1857-1861 - Stijn Ringeling
Cancellation of Quantization Noise in Sigma Delta Modulators Through Modeling of Non-Linearities. 1862-1866 - Omobayode Fagbohungbe
Assessing the Performance of Analog Training for Transfer Learning. 1867-1871 - Hengtan Zhang
A Dual-Mode Neuromorphic Controller With On-Chip Learning for Robot Motion Control. 1872-1876 - David Simpson
Smart Watchdog for RISC-V: A Novel Spiking Neural Network Approach to Fault Detection. 1877-1881 - Qi-Xian Wu
A Low-Complexity and Reconfigurable Design for Nonlinear Function Approximation in Transformers. 1882-1886 - Äantas Kesten
Halfbex: RISC-V Narrow Data Path Optimization for Energy Reduction. 1887-1891 - Daniel Casanueva-Morato
Toward a Dynamic Closed-Loop Neuromorphic Trajectory Interpolation Model: Hardware Emulation and Software Simulation. 1892-1896 - Jonathan Andree
A Behavioral Model for High-Speed 4:1 Analog Multiplexers, Utilizing Stochastic Modelfitting. 1897-1901 - Wenshuang Liu, Jie Yang
SVG Configuration Scheme to Enhance Renewable Energy Accommodation Considering Voltage Stability Constraints in Renewable Power Grids. 1902-1906 - Yue Zhong
A Three-Phase Fully-Integrated Reconfigurable Switched-Capacitor Converter for Near-Threshold Computing. 1907-1911 - Michelangelo Orabona
High Time-Resolution PWM Generator for GaN Converters. 1912-1916 - Qitong Pu
A Time Skew Calibration Technique With Fast Convergence for Time-Interleaved ADCs Based on Windowed Autocorrelation Algorithm. 1917-1921 - Xianghui Zhang
A MASH SAR ADC With Nonlinearity Error Shaping Achieving 101.6-dB SFDR and 83.6-dB SNDR. 1922-1926 - Ilaria Ferrari
An Analysis of Switch Thermal Noise in SAR Converters. 1927-1931 - Minhyeok Son
A Low-Offset Operational Amplifier Using Multipath Ping-Pong Current Adjusting Auto-Zeroing Stabilization Technique. 1932-1936 - Yigi Kwon
A 10-GS/s 6-bit 0.014 mm2 Switched-Capacitor DAC with Clock-Free DAC Core in 28-nm CMOS. 1937-1941 - Zhenhao Fan
A 15-bit BW/Power Scalable Pseudo-Pseudo-Differential MASH ADC Using an Adaptively Biased Inverter Amplifier. 1942-1946 - Peilong Lin
A 0.4-V 0.92-nW 20-kHz Fully-Bias-Free FLL Using Time-Domain Operational Amplifier With Self-Adaptive Charge-Sharing Integrator. 1947-1951 - Ke Li
A Theoretical Study on the Fundamental Amplitude Stability of the Stepwise-Approximated Sine Wave in the Sine Carrier Generator Based on DDS. 1952-1956 - Dengquan Li
FR-CNN: Frequency Recognition Convolutional Neural Network-Based Calibration for Timing Skew in TI-ADCs. 1957-1961 - Yuan Chun Li
A 16.5-to-37.9 GHz Quad-Core Quad-Mode VCO With Compact 0.07 mm2 in 65-nm CMOS. 1962-1966 - Chun Yang
A 29-Gb/s D-Band Gain-Boosted OOK Modulator With 60-dB On-Off Ratio in 28-nm CMOS. 1967-1971 - Sayan Kumar
Asymmetry Effects on Thermal and Flicker Phase Noise of Rotary Traveling-Wave Oscillators. 1972-1976 - Taeho Shin
A Driver-Current-Regulated 120-Gb/s PAM-8 7-bit DAC-Based Transmitter in 28-nm CMOS. 1977-1981 - Jiahan Fu
A 32-QAM 50-Gbps D-Band Receiver RF Front-End With IF Bandwidth Extension. 1982-1986 - Yewei Yu
Finite-Iteration Learning Tracking Control of Magnetic Shape Memory Alloy Actuator Based on Neural Network. 1987-1991 - Ning Zhou
Neural Network-Aided Sampled-Data Control for a Class of Nonlinear Systems With Unknown Dynamics. 1992-1996 - Xinhai Zhuang
Distributed Optimal Secondary Control of Microgrids: A Consensus-Driven Hierarchical Algorithm With Predefined-Time Convergence. 1997-2001 - Xinyi Li
NMIX: NoC-Aware Mixed Precision Quantization for Energy-Efficient ML Accelerator. 2002-2006 - Siwei Xiang, Yu Gao, Yishuo Meng, Jianfei Wang
A Self-Organizing Linked Storage Architecture With Dynamic Partition Achieving High Capacity Utilization. 2007-2011 - Zhengqing Zhong
MorphBungee-Tiny: An Ultra-Low-Cost FPGA Implementation of Neuromorphic Architecture With High-Accuracy On-Chip E-Prop Learning. 2012-2016 - Junyan Zhang
A 1-8 b Reconfigurable 64 Mb STT-MRAM Near-Memory Computing Macro for Energy-Efficient AI-Edge Devices. 2017-2021 - Seunghyun Moon
DeltaTrack: Flow-Driven Multiple Object Tracking Accelerator With Variable LSB Approximation for Real-Time and Energy-Efficient Video Analytics. 2022-2026 - Gianluca Leone
ESTU: Enabling Spiking Transformers on Ultra-Low-Power FPGAs. 2027-2031 - Richelle L. Smith
Computing Max 3-Cut With CMOS Tripolar Oscillatory Cellular Neural Networks. 2032-2036 - Cameron M. Pike
Accurate Prediction of Nonlinear Distortion of Multi-Carrier Signals. 2037-2041 - Donghun Kim
A 12-MHz GaN-Based DC-DC Buck Converter Featuring Dual Reverse Conduction Controllers. 2042-2046 - Samuel S. Queiroz
LLC Resonant Converter With Reconfigurable Secondary-Side for Output Voltage Regulation. 2047-2051 - Donghai Zhu
Optimized Power Decoupling Control for Grid-Forming Converter Under Different R/X Ratios of Grid Impedance. 2052-2056 - Philippe Bich
MESA: A Dynamical Attention-Based Pre-Processing Pipeline for High-Throughput Event-Based Computer Vision Tasks. 2057-2061
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