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Journal of Electronic Testing, Volume 35
Volume 35, Number 1, February 2019
- Vishwani D. Agrawal:
Editorial. 1-2 - New Editors - 2019. 3-4
- 2018 JETTA Reviewers. 5-6
- Test Technology Newsletter. 7-8
- Paulo Ricardo Cechelero Villa
, Rodrigo Travessini, Roger C. Goerl, Fabian Luis Vargas, Eduardo Augusto Bezerra:
Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy. 9-27 - Serhiy Avramenko
RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems. 29-44 - Rahma Ben Fraj, Vincent Beroulle, Nicolas Fourty, Aref Meddeb:
An Optimized NS2 Module for UHF Passive RFID Systems. 45-58 - Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. 59-75 - Shakeel Ahmad
Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test. 77-85 - Andres F. Gomez, Víctor H. Champac:
An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects. 87-100 - Marek Cieplucha
Metric-Driven Verification Methodology with Regression Management. 101-110 - Haibin Wang
A Layout-Based Rad-Hard DICE Flip-Flop Design. 111-117 - Shiva Taghipour, Rahebeh Niaraki Asli
Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops. 119-125
Volume 35, Number 2, April 2019
- Vishwani D. Agrawal:
Editorial. 127-128 - Test Technology Newsletter. 129-130
- Remesh Kumar K. R
Testing of Current Carrying Capacity of Conducting Tracks in High Power Flexible Printed Circuit Boards. 131-143 - Maha Kooli, Giorgio Di Natale, Alberto Bosio
Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems. 145-162 - Shuo Cai, Weizheng Wang, Fei Yu
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. 163-172 - Alexandra Kourfali
An Integrated on-Silicon Verification Method for FPGA Overlays. 173-189 - G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen:
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects. 191-200 - Omid Ranjbar, Siavash Bayat Sarmadi, Fatemeh Pooyan, Hossein Asadi:
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. 201-214 - Biswajit Bhowmik
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. 215-243 - Djiddo Ali Oumar, Mahamat Issa Boukhari, M. A. Taha, Stéphane Capraro
Characterization Method for Integrated Magnetic Devices at Lower Frequencies (up to 110 MHz). 245-252 - Martin Omaña, S. Govindaraj, Cecilia Metra:
Low-Cost Strategy for Bus Propagation Delay Reduction. 253-260 - Marco Grossi
Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers. 261-267
Volume 35, Number 3, June 2019
- Vishwani D. Agrawal:
Editorial. 269-270 - Test Technology Newsletter. 271-272
- Sophie Dupuis
Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. 273-291 - Yongkang Tang
Activity Factor Based Hardware Trojan Detection and Localization. 293-302 - Mahroo Zandrahimi
Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS. 303-315 - Rahul Kundu
A Distributed Error and Anomaly Communication Architecture for Analog and Mixed-Signal Systems. 317-334 - Maryam Shafiee
Contact-Less Near-Field Test of Active Integrated RF Phased Array Antennas. 335-347 - S. Herasimov
Testing Signals for Electronics: Criteria for Synthesis. 349-357 - Haider Al-kanan
Saleh Model and Digital Predistortion for Power Amplifiers in Wireless Communications Using the Third-Order Intercept Point. 359-365 - Gennaro Severino Rodrigues
Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection. 367-381 - S. Geetha
Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique. 383-400 - Ali Hajian, Saeed Safari:
Modeling Soft Error Propagation in Near-Threshold Combinational Circuits Using Neural Networks. 401-412 - Jiaqiang Li, Pedro Reviriego, Liyi Xiao
Low Delay 3-Bit Burst Error Correction Codes. 413-420
Volume 35, Number 4, August 2019
- Vishwani D. Agrawal:
Editorial. 421-422 - Test Technology Newsletter. 423-424
- Breeta SenGupta, Dimitar Nikolov, Assmitra Dash, Erik Larsson
Test Flow Selection for Stacked Integrated Circuits. 425-440 - Mousum Handique, Santosh Biswas
Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions. 441-457 - Chung-Huang Yeh
Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements. 459-472 - Princy P
An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM. 473-483 - Shyue-Kung Lu
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. 485-495 - A. Kavitha
16- Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR Analysis. 497-517 - Dragan Lambic
Security Analysis and Improvement of the Pseudo-random Number Generator Based on Piecewise Logistic Map. 519-527 - Yanjiang Liu
Hardware Trojan Detection Leveraging a Novel Golden Layout Model Towards Practical Applications. 529-541 - Kokila Jagadeesh
Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs. 543-558 - JungHo Kang
Connectivity Test for System in Package Interconnects. 559-565 - Yunpeng Zhang
Electromagnetic Parameters Measurement of Sheet Using Separate Microstrip Line. 567-572
Volume 35, Number 5, October 2019
- Vishwani D. Agrawal:
Editorial. 573 - 2018 JETTA-TTTC Best Paper Award. 575-576
- Test Technology Newsletter. 577-578
- Kanad Basu, Mingsong Chen, Rubin A. Parekhji:
Guest Editorial. 579-580 - Arjun Singh Chauhan, Vineet Sahula
Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness. 581-601 - Arjun Singh Chauhan, Vineet Sahula
Correction to: Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness. 603-604 - Rajat Sadhukhan
Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs. 605-619 - Richa Agrawal, Ranga Vemuri
A State Machine Encoding Methodology Against Power Analysis Attacks. 621-639 - Bodhisatwa Mazumdar, Soma Saha, Ghanshyam Bairwa, Souvik Mandal
Classical Cryptanalysis Attacks on Logic Locking Techniques. 641-654 - Binod Kumar
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. 655-678 - Rajeswari Devadoss
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority. 679-694 - Vasudevan Madampu Suryasarman, Santosh Biswas
RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing. 695-714 - Pradeep Kumar Biswal, Santosh Biswas
A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements. 715-727 - Shukla Banik
An Integrated Framework for Application Independent Testing of FPGA Interconnect. 729-740 - Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri:
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing. 741-759
Volume 35, Number 6, December 2019
- Vishwani D. Agrawal:
Editorial. 761-763 - The Newsletter of the Test Technology Technical Council of the IEEE Computer Society. 765-766
- Yiming Ouyang, Qi Wang, Lizhu Hu, Huaguo Liang:
DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip. 767-777 - Ayan Palchaudhuri
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations. 779-796 - Chuang Yang, Feng Feng
Multi-Step-Ahead Prediction for a CMOS Low Noise Amplifier Aging Due to NBTI and HCI Using Neural Networks. 797-808 - Thomas Moon
Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition. 809-822 - Omar Al-Terkawi Hasib
Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics. 823-838 - Seyed Mohammad Sebt, Ahmad Patooghy, Hakem Beitollahi
An Efficient Technique to Detect Stealthy Hardware Trojans Independent of the Trigger Size. 839-852 - Weize Yu
Leveraging Balanced Logic Gates as Strong PUFs for Securing IoT Against Malicious Attacks. 853-865 - Matheus Monteiro Mariano
Comparing Graph-Based Algorithms to Generate Test Cases from Finite State Machines. 867-885 - Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. 887-900 - Anusha Gorantla
Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications. 901-907 - Xixi Dai, Haibin Wang
A Single Event Upset Resilient Latch Design with Single Node Upset Immunity. 909-916 - Bo Zhou
Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs. 917-923
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