default search action
VLSI Circuits 2019: Kyoto, Japan
- 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. IEEE 2019, ISBN 978-4-86348-720-8
- Stefano Bianchi, I. Muñoz-Martín, Giacomo Pedretti, Octavian Melnic, Stefano Ambrogio, Daniele Ielmini:
Energy-efficient continual learning in hybrid supervised-unsupervised neural networks with PCM synapses. 1-2 - Takeji Fujibayashi, Yohsuke Takeda:
A 76- to 81-GHz, 0.6° rms Phase Error Multi-channel Transmitter with a Novel Phase Detector and Compensation Technique. 16- - Yukun Zhu
, Pranith R. Byreddy, Kenneth K. O, Wooyeol Choi
426-GHz Imaging Pixel Integrating a Transmitter and a Coherent Receiver with an Area of 380×47μm2 in 65-nm CMOS. 18- - Shiyu Su, Mike Shuo-Wei Chen:
A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. 20- - ChandraKanth R. Chappidi
A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications. 22- - Jungwoon Park, Junyoung Jang, Geunhaeng Lee, Hyunmin Koh, Changhwan Kim, Tae Wook Kim:
A Time Domain Artificial Intelligence Radar for Hand Gesture Recognition Using 33-GHz Direct Sampling. 24- - Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. 28- - Austin Rovinski, Chun Zhao
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. 30- - Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. 32- - Paul N. Whatmough, Sae Kyu Lee, Marco Donato, Hsea-Ching Hsueh, Sam Likun Xi, Udit Gupta
A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators. 34- - Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang, Atsushi Shirane, Kenichi Okada
0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. 38- - Xiaolong Liu, Howard C. Luong:
A 270-Ghz Fully-Integrated Frequency Synthesizer in 65nm CMOS. 40- - Yi-An Li, Ali M. Niknejad:
A 138Fsrms-Integrated-Jitter and -249dB-FoM Clock Multiplier with -51dBc Spur Using A Digital Spur Calibration Technique in 28-nm CMOS. 42- - Xiaodong Meng, Xing Li, Xiaopeng Zhong, Yuan Yao, Chi-Ying Tsui, Wing-Hung Ki
A 2.2μW 600kHz Frequency-Locked Relaxation Oscillator with 0.046%/V Voltage and 48.69ppm/°C Temperature Stability for IoT Sensor Node Applications. 44- - Takahiko Ishizu, Yuto Yakubo, Kazuma Furutani, Atsuo Isobe, Masashi Fujita, Tomoaki Atsumi, Yoshinori Ando, Tsutomu Murakawa, Kiyoshi Kato, Masahiro Fujita, Shunpei Yamazaki:
A 48 MHz 880-nW Standby Power Normally-Off MCU with 1 Clock Full Backup and 4.69-μs Wakeup Featuring 60-nm Crystalline In-Ga-Zn Oxide BEOL-FETs. 48- - Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De:
A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. 50- - Juan Sebastian Piedrahita Giraldo, Steven Lauwereins, Komail M. H. Badami, Hugo Van hamme, Marian Verhelst
18μW SoC for near-microphone Keyword Spotting and Speaker Verification. 52- - Joao Pedro Cerqueira, Thomas J. Repetti, Yu Pu, Shivam Priyadarshi, Martha A. Kim, Mingoo Seok:
Catena: A 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for Mobile and Embedded Computing. 54- - Qiuyang Lin, Jiawei Xu, Shuang Song
A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors. 58- - Hyeonho Han, Woojun Choi, Youngcheol Chae:
A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. 60- - Doohwan Jung, Jong Seok Park, Gregory Villiam Junek, Sandra Ivonne Grijalva, Sagar R. Kumashi, Adam Y. Wang
A 21952-Pixel Multi-Modal CMOS Cellular Sensor Array with 1568-Pixel Parallel Recording and 4-Point Impedance Sensing. 62- - Umidjon Nurmetov, Tobias Fritz, Ernst Müllner, Christopher M. Dougherty, Franz Kreupl
A CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution. 64- - Chen-Kai Hsu, Nan Sun:
A 75.8dB-SNDR Pipeline SAR ADC with 2nd-order Interstage Gain Error Shaping. 68- - Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu:
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range. 70- - Min-Jae Seo
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. 72- - Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. 74- - Mingqiang Guo
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. 76- - Richard Dorrance
An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba. 80- - Hechen Wang
A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation. 82- - Bob Wiser, Kannan A. Sankaragomathi, Justin Schauer, Sean Korhummel, Pouya Kavousian, Daniel J. Yeager, Nivi Arumugam, Nate Pletcher, David Barkin, Reed Parker, Lori Callaghan, Richard C. Ruby, Brian Otis:
A 1.53 mm3 crystal-less standards-compliant Bluetooth Low Energy module for volume constrained wireless sensors. 84- - Jesse Moody, Anjana Dissanayake
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver. 86- - Filip Maksimovic, Brad Wheeler, David C. Burnett
A Crystal-Free Single-Chip Micro Mote with Integrated 802.15.4 Compatible Transceiver, sub-mW BLE Compatible Beacon Transmitter, and Cortex M0. 88- - Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh:
A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. 92- - Han-Gon Ko, Soyeong Shin
A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. 94- - Kwanyeob Chae, JongRyun Choi, Hyungkwon Lee, Jinho Choi, Shinyoung Yi, Yoonjee Nam, Sangyun Hwang, Joohyung Lee, Won Lee, Kihwan Seong, Joohee Shin, Soo-Min Lee, Seokkyun Ko, Jihun Oh, Billy Koo, Sanghune Park, Jongshin Shin, Hyungjong Ko:
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. 96- - Cagla Cakir, Andy W. Chen, Y. K. Chong, Sriram Thyagarajan, Mark P. McCartney, Peixuan Tan, Yulin Shi, Mudit Bhargava:
A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms. 112- - Jin-Seok Heo, Kihan Kim, Dong-Hoon Lee, Chang-Kyo Lee, Daesik Moon, Kiho Kim, Jin-Hyeok Baek, Sung-Woo Yoon, Hui-Kap Yang, Kyungryun Kim, Youngjae Kim, Bokgue Park, Su-Jin Park, Joung-Wook Moon, Jae-Hyung Lee, Yun-Sik Park, Soobong Jang, Seok-Hun Hyun, Hyuck-Joon Kwon, Jung-Hwan Choi, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee:
A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. 114- - Chun Shiah, C. N. Chang, Richard Crisp, C. P. Lin, C. N. Pan, C. P. Chuang, H. L. Chen, S. H. Jheng, T. F. Chang, W. J. Huang, K. C. Ting, Rick Dai, W. M. Huang, Bor-Doou Rong, Nicky Lu:
A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems. 116- - Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. 118- - Ruiqi Guo
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS. 120- - Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. 124- - Keith A. Bowman
A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. 126- - Sourav Dutta, A. Khanna, Wriddhi Chakraborty, J. Gomez, S. Joshi, Suman Datta
Spoken vowel classification using synchronization of phase transition nano-oscillators. 128- - Sung Justin Kim, Dongkwun Kim, Yu Pu, Chunlei Shi, Mingoo Seok:
A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator System for Supporting a Large Digital Load. 128- - Jeonghyun Lee
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer. 130- - Dong-Kyu Kim, Hyun-Sik Kim:
A 300mA BGR-Recursive Low-Dropout Regulator Achieving 102-to-80dB PSR at Frequencies from 100Hz to 0.1MHz with Current Efficiency of 99.98%. 132- - Hung-Yi Huang, Tai-Haur Kuo:
A 0.07mm2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation. 136- - Woo-Cheol Kim, Dong-Shin Jo, Yi-Ju Roh, Ye-Dam Kim
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. 138- - Xiyuan Tang, Begum Kasap
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. 140- - Inhee Lee, David T. Blaauw:
A 31 pW-to-113 nW Hybrid BJT and CMOS Voltage Reference with 3.6% ±3σ-inaccuracy from 0○C to 170 ○C for Low-Power High-Temperature IoT Systems. 142- - Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun:
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. 144- - Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka:
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. 148- - Subhankar Pal
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. 150- - Po-Han Chen, Shu-Wen Yang, Shih-Yao Huang, Li-De Chen, Chao-Tsung Huang:
A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications. 154- - Zhao Zhang, Guang Zhu, C. Patrick Yue:
A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps. 158- - Takahisa Tanaka, K. Tabuchi, Kohei Tatehora, Yohsuke Shiiki, S. Nakagawa, Tsunaki Takahashi
Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets. 158- - E-San Jang
Record-High Performance Trantenna Based On Asymmetric Nano-Ring Fet For Polarization-Independent Large-Scale/Real-Time Thz Imaging. 160- - Ji-Hwan Seol, Dennis Sylvester, David T. Blaauw, Tae-Kwang Jang
A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur. 160- - Jingcheng Tao, Chun-Huat Heng:
A 2.2-GHz 3.2-mW DTC-free Sampling ΔΣ Fractional-N PLL with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc Reference Spur. 162- - Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS. 164- - Kea-Tiong Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Chun Kuo, Tai-Hsing Wen, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Meng-Fan Chang:
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. 166- - Todd Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang:
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper). 168- - Abu Sebastian
Computational memory-based inference and training of deep neural networks. 168- - Dong Yan, Xugang Ke, Dongsheng Brian Ma:
A Two-Phase 2MHz DSD GaN Power Converter with Master-Slave AO2T Control for Direct 48V/1V DC-DC Conversion. 170- - Kang Wei, Bumkil Lee, Dongsheng Brian Ma:
A 10-MHz 14.3W/mm2 DAB Hysteretic Control Power Converter Achieving 2.5W/247ns Full Load Power Flipping and above 80% Efficiency in 99.9% Power Range for 5G IoTs. 172- - Yen-An Lin, Tzu-Ping Huang, You-Zheng Ou-Yang, Zheng-Ru Wu, Ke-Horng Chen
A Right-Half-Plane Zero-Free Buck-Boost DC-DC Converter with 97.46% High Efficiency and Low Output Voltage Ripple. 174- - Longyang Lin, Saurabh Jain, Massimo Alioto:
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW. 178- - Inhee Lee, Eunseong Moon, Yejoong Kim, Jamie Phillips, David T. Blaauw:
A 10mm3 Light-Dose Sensing IoT2 System With 35-To-339nW 10-To-300klx Light-Dose-To-Digital Converter. 180- - Patrick O'Connor, Casey Meekhof, Chad McBride, Christopher Mei, Cyrus S. Bamji, Dave Rohn, Hakon Strande, Justin Forrester, Mike Fenton, Ryan Haraden, Tolga Ozguner, Travis Perry:
Custom Silicon and Sensors Developed for a 2nd Generation Mixed Reality User Interface. 186- - Shosuke Fujii, Reika Ichihara, Takuya Konno, Marina Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Yoko Yoshimura, Masumi Saitoh, Masato Koyama:
Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication. 188- - Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET. 190- - William J. Gallagher, Eric Chien, Tien-Wei Chiang, Jian-Cheng Huang, Meng-Chun Shih, C. Y. Wang, Christine Bair, George Lee, Yi-Chun Shih, Chia-Fu Lee, Roger Wang, Kuei-Hung Shen, J. J. Wu, Wayne Wang, Harry Chuang:
Recent Progress and Next Directions for Embedded MRAM Technology. 190- - Nandish Mehta
A Laser-forwarded Coherent 10Gb/s BPSK Transceiver using Monolithic Microring Resonators in 45nm SOI CMOS. 192- - Paola Zuliani, A. Conte, P. Cappelletti:
The PCM way for embedded Non Volatile Memories applications. 192- - Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. 194- - Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. 194- - Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS. 196- - Jinhyung Lee, Kwangho Lee, Hyojun Kim
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level. 198- - Ken Matsubara, Tsutomu Nagasawa, Yoshinobu Kaneda, Hidenori Mitani, Hiroshi Sato, Takashi Iwase, Yasunobu Aoki, Keiichi Maekawa, Hideaki Yamakoshi, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications. 202- - Fabio Disegni, Roberto Annunziata, A. Molgora, G. Campardo, Paolo Cappelletti, P. Zuliani, P. Ferreira, A. Ventre, G. Castagna, Andreia Cathelin, Anna Gandolfo, F. Goller, S. Malhi, D. Manfrè, Alfonso Maurelli, C. Torti, Franck Arnaud, M. Carfì, M. Perroni, M. Caruso, S. Pezzini, G. Piazza, Olivier Weber, M. Peri:
Embedded PCM macro for automotive-grade microcontroller in 28nm FD-SOI. 204- - Yue Zha
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications. 206- - E. R. Hsieh, C. W. Chang, C. C. Chuang, H. W. Chen, Steve S. Chung:
The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond. 208- - Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono:
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive. 210- - Injun Park, Woojin Jo, Chanmin Park, Byungchoul Park, Jimin Cheon, Youngcheol Chae:
A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition. 214- - Chenghan Li, Luca Longinotti, Federico Corradi
A 132 by 104 10μm-Pixel 250μW 1kefps Dynamic Vision Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression. 216- - Seung-Hoon Ko:
An Automatic Ear Detection Technique in Capacitive Sensing Readout IC Using Cascaded Classifiers and Hovering function. 218- - Jing Li, Zhao Chen, Mingliang Tan
A 1.54mW/Element 150μm-Pitch-Matched Receiver ASIC with Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D Ultrasound Probes. 220- - Burak Gönen, Shoubhik Karmakar, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
A Low Power Continuous-Time Zoom ADC for Audio Applications. 224- - Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan:
A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. 226- - Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang:
A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS. 228- - Pierluigi Cenci, Muhammed Bolatkale, Robert Rutten, M. Ganzerli, Gerard Lassche, Kofi A. A. Makinwa, Lucien J. Breems:
A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. 230- - Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. 234- - Weiwei Shan, Ao Fan, Jiaming Xu, Jun Yang, Mingoo Seok:
A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS. 236- - Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. 238- - Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang
A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. 240- - Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose:
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2. 248- - Mial E. Warren:
Automotive LIDAR Technology. 254- - Byungchoul Park, Injun Park, Woojun Choi, Youngcheol Chae:
A 64×64 APD-Based ToF Image Sensor with Background Light Suppression up to 200 klx Using In-Pixel Auto-Zeroing and Chopping. 256- - Min-Sun Keel, Young-Gu Jin, Youngchan Kim, Daeyun Kim, Yeomyung Kim, Myunghan Bae, Bumsik Chung, Sooho Son, Hogyun Kim, Taemin An, Sung-Ho Choi, Taesub Jung, Yonghun Kwon, Sungyoung Seo, Sae-Young Kim, Kwanghyuk Bae, Seung-Chul Shin, Myoungoh Ki, Chang-Rok Moon, Hyunsurk Ryu:
A 640×480 Indirect Time-of-Flight CMOS Image Sensor with 4-tap 7-μm Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation Scheme. 258- - Tarek Al Abbas, Oscar Almer, Sam W. Hutchings, Ahmet T. Erdogan
A 128×120 5-Wire 1.96mm2 40nm/90nm 3D Stacked SPAD Time Resolved Image Sensor SoC for Microendoscopy. 260- - Pavan Bhargava, Taehwan Kim, Christopher V. Poulton, Jelena Notaros, Ami Yaacobi, Erman Timurdogan, Christopher Baiocco, Nicholas Fahrenkopf, Seth Kruger, Tat Ngai, Yukta Timalsina, Michael R. Watts, Vladimir Stojanovic:
Fully Integrated Coherent LiDAR in 3D-Integrated Silicon Photonics/65nm CMOS. 262- - Yoel Krupnik
112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process. 266- - Jeongho Hwang
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. 268- - Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, Robert Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, Fred Kuo, Wei-Li Chen, Tae Young Goh, Kenny Hsieh:
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET. 270- - Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh:
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. 272- - Can Wang
A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. 274- - Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami:
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. 278- - Taeju Lee, Jee-Ho Park
A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca2+-Probe-Based Fluorescence Recording and Electrical Recording. 290- - Yeseul Jeon, Chongsoo Jung, Song-I Cheon, Hyungjoo Cho, Ji-Hoon Suh, Hyuntak Jeon, Seok-Tae Koh, Minkyu Je:
A 100Mb/s Galvanically-Coupled Body-Channel-Communication Transceiver with 4.75pJ/b TX and 26.8 pJ/b RX for Bionic Arms. 292- - Cheonhoo Jeon, Jahyun Koo, Kyongsu Lee
A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna. 294- - Xiaolin Yang, Jiawei Xu, Hosung Chun, Marco Ballini
A 108dB DR Hybrid-CTDT Direct-Digitalization ΔΣ-ΣM Front-End with 720mVpp Input Range and >300mV Offset Removal for Wearable Bio-Signal Recording. 296- - Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. 300- - Juhyoung Lee, Dongjoo Shin, Jinsu Lee, Jinmook Lee, Sanghoon Kang, Hoi-Jun Yoo:
A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices. 302- - Donghyeon Han, Jinsu Lee, Jinmook Lee, Hoi-Jun Yoo:
A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture. 304- - Jie-Fang Zhang
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. 306- - Taewook Kang, Inhee Lee, Sechang Oh, Tae-Kwang Jang
A 1.74.12 mm3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation. 310- - Jun-Chau Chien, Peter L. Mage, H. Tom Soh, Amin Arbabian:
An Aptamer-based Electrochemical-Sensing Implant for Continuous Therapeutic- Drug Monitoring in vivo. 312- - Ali Ameri, Luya Zhang
A 114GHz Biosensor with Integrated Dielectrophoresis for Single Cell Characterization. 314- - Da Ying, Ping-Wei Chen, Chi Tseng, Yu-Hwa Lo, Drew A. Hall
A Sub-pA Current Sensing Front-End for Transient Induced Molecular Spectroscopy. 316- - Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki
A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques. 320- - Cheng-Yen Lee, Tzu-Ping Huang, Ke-Horng Chen
A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protection. 322- - Shuo Li, Abhishek Roy, Benton H. Calhoun:
A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency. 324- - Inho Park, Junyoung Maeng, Minseob Shim, Junwon Jeong, Chulwoo Kim:
A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency. 326-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-31 20:03 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: