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ESSCIRC 2008: Edinburgh, Scotland, UK
- William Redman-White, Anthony J. Walton:
ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. IEEE 2008, ISBN 978-1-4244-2361-3 - Robert S. Chau:
Emerging device nanotechnology for future high-speed and energy-efficient VLSI: Challenges and opportunities. 1-3 - Paolo Fiorini, Inge Doms, Chris Van Hoof
, Ruud J. M. Vullers
Micropower energy scavenging. 4-9 - Takayasu Sakurai:
Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future. 10-16 - Vivek Subramanian
Printed electronics for low-cost electronic systems: Technology status and application development. 17-24 - Yoshiaki Daimon Hagihara:
SOI design in Cell Processor and beyond. 25-31 - S. Jensen, G. Molnar, Jon Giftakis, Wesley Santa, Randy Jensen, Dave Carlson, M. Lent, Timothy Denison
Information, energy, and entropy: Design principles for adaptive, therapeutic modulation of neural circuits. 32-39 - Marco Berkhout, Lucien J. Breems, Ed van Tuijl:
Audio at low and high power. 40-49 - Sungdae Choi, Katsuyuki Ikeuchi, Hyunkyung Kim, Kenichi Inagaki, Masami Murakata, Nobuyuki Nishiguchi, Makoto Takamiya, Takayasu Sakurai:
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node. 50-53 - Vasudha Gupta, Mohab Anis:
Area/yield trade-offs in scaled CMOS SRAM cell. 54-57 - Ling Su, Dongsheng Ma, A. Paul Brokaw:
A monolithic step-down SC power converter with frequency-programmable subthreshold z-domain DPWM control for ultra-low power microsystems. 58-61 - Mike Wens, Michiel Steyaert
A fully-integrated 130nm CMOS DC-DC step-down converter, regulated by a constant on/off-time control system. 62-65 - Jente B. Kuang, Abraham Mathews, John Barth, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM. 66-69 - Poki Chen, Kai-Ming Wang, Yu-Han Peng, Yu-Shin Wang, Chun-Chi Chen:
A time-domain SAR smart temperature sensor with -0.25∼+0.35°C inaccuracy for on-chip monitoring. 70-73 - S. Mahdi Kashmiri, Sha Xia, Kofi A. A. Makinwa:
A temperature-to-digital converter based on an optimized electrothermal filter. 74-77 - Andrea Lombardi, Marco Grassi
A fully integrated interface circuit for 1.5°C accuracy temperature control and 130-dB dynamic-range read-out of MOX gas sensors. 78-81 - Dongsuk Shin, Won-Joo Yun, Hyun-Woo Lee, Young-Jung Choi, Suki Kim, Chulwoo Kim:
A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. 82-85 - Behzad Mesgarzadeh, Atila Alvandpour:
A 2-GHz 7-mW digital DLL-based frequency multiplier in 90-nm CMOS. 86-89 - Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic
A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. 90-93 - Shih-An Yu, Peter R. Kinget
A 0.042-mm2 fully integrated analog PLL with stacked capacitor-inductor in 45nm CMOS. 94-97 - Hiroyuki Ito, Hasnain Lakdawala, Ashoke Ravi, Stefano Pellerano, Rick Ruby, Krishnamurthy Soumyanath, Kazuya Masu
A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. 98-101 - Nobuhiro Shiramizu, Toru Masuda, Takahiro Nakamura, Katsuyoshi Washio:
24-GHz 1-V pseudo-stacked mixer with gain-boosting technique. 102-105 - Romaric Toupe, Yann Deval
A 65-nm CMOS 8-GHz injection locked oscillator for HDR UWB applications. 106-109 - Ullrich R. Pfeiffer
A 600-GHz CMOS focal-plane array for terahertz imaging applications. 110-113 - Cristiano Niclass
Single-photon synchronous detection. 114-117 - Daniel Durini
Highly sensitive UV-enhanced linear CMOS photosensor. 118-121 - Nader Safavian, Karim S. Karim, Arokia Nathan, John A. Rowlands:
A 3-TFT hybrid active-passive pixel with correlated double sampling CMOS readout circuit for real-time medical x-ray imaging. 122-125 - Jeremy D. Schaub, Fadi H. Gebara, Tuyet Nguyen, Ivan Vo, Jarom Peña, Dhruva J. Acharyya:
On-chip jitter and oscilloscope circuits using an asynchronous sample clock. 126-129 - Daniele Puntin, Stefano Stanzione, Giuseppe Iannaccone
CMOS unclonable system for secure authentication based on device variability. 130-133 - Sanjay Pant, David T. Blaauw:
Circuit techniques for suppression and measurement of on-chip inductive supply noise. 134-137 - Edith Beigné
A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs. 138-141 - Hiroshi Yoshida, Takehiko Toyoda, T. Yasuda, Yosuke Ogasawara, M. Ishii, T. Murasaki, Gaku Takemura, Masaomi Iwanaga, T. Takida, Yuta Araki, T. Hashimoto, K. Sami, Teruo Imayama, H. Shimizu, Hideyuki Kokatsu, Y. Tsuda, I. Tamura, H. Masuoka, Masahiro Hosoya, R. Ito, Hidenori Okuni, T. Kato, K. Sato, K. Nonin, K. Osawa, R. Fujimoto, S. Kawaguchi, Hiroshi Tsurumi, N. Itoh:
A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface. 142-145 - Marco Cassia, Aristotele Hadjichristos, Hong Sun Kim, Jin-Su Ko, Jeongsik Yang, Sang-Oh Lee, Kamal Sahota:
A low power CMOS SAW-less quad band WCDMA/HSPA/1X/EGPRS transmitter. 146-149 - Reza Yousefi, Ralph Mason:
A 14-mW 2.4-GHz CMOS transceiver for short range wireless sensor applications. 150-153 - Kenneth Barnett, Harish Muthali, Susanta Sengupta, Yunfei Feng, Bo Yang, Zhije Xiong, Tae Wook Kim, James Jaffee, Cormac Conroy:
A multi-standard mobile digital video receiver in 0.18μm CMOS process. 154-157 - Olivier Jamin, Vincent Rambeau, Frederic Mercier, Insaf Meliane:
On-chip auto-calibrated RF tracking filter for cable silicon tuner. 158-161 - Filip Tavernier, Michiel Steyaert
Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode. 162-165 - George von Büren, Lucio Rodoni, Heinz Jäckel, Roland Brun, Daniel Holzer, Alex Huber, Martin L. Schmatz:
5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS. 166-169 - William Redman-White, Martin Bugbee, Steve Dobbs, Xinyan Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten:
A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery. 170-173 - Takashi Kawamoto, Masaru Kokubo:
A low-jitter 1.5-GHz and 350-ppm spread-spectrum serial ATA PHY using reference clock with 400-ppm production-frequency tolerance. 174-177 - Ori Eshet, Adee Ran, Amir Mezer, Yaniv Hadar, Dror Lazar, Miki Moyal:
An adaptive 4-tap analog FIR equalizer for 10-Gb/s over backplane serial link receiver. 178-181 - Mark A. Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar:
A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. 182-185 - Yoonmyung Lee
Standby power reduction techniques for ultra-low power processors. 186-189 - Claude Arm, Steve Gyger, Jean-Marc Masgonty, Marc Morgan, Jean-Luc Nagel, Christian Piguet, Flavio Rampogna, Patrick Volet:
Low-power 32-bit dual-MAC 120 μW/MHz 1.0 V icyflex DSP/MCU core. 190-193 - KyungHoon Kim, SangSic Yoon, KiChang Kwean, DaeHan Kwon, SunSuk Yang, MunPhil Park, YongKi Kim, ByongTae Chung:
A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network. 194-197 - Guido De Sandre, Luca Bettini, Emanuela Calvetti, G. Giacomi, Marco Pasotti, Massimo Borghi, Paola Zuliani, Roberto Annunziata, I. Tortorelli, Fabio Pellizzer, Roberto Bez:
Program circuit for a phase change memory array with 2 MB/s write throughput for embedded applications. 198-201 - Parmoon Seddighrad, Ashoke Ravi, Masoud Sajadieh, Hasnain Lakdawala, Krishnamurthy Soumyanath:
A 3.6GHz, 16mW ΣΔ DAC for a 802.11n / 802.16e transmitter with 30dB digital power control in 90nm CMOS. 202-205 - Ahmed Gharbiya, David A. Johns:
A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator. 206-209 - Karthikeyan Reddy, Shanthi Pavan:
A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range. 210-213 - Pieter Palmers, Michiel Steyaert
A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm. 214-217 - Edoardo Bonizzoni, Aldo Pena-Perez, Franco Maloberti, Miguel Angel Garcia-Andrade:
Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW. 218-221 - Riaz Naseer, Jeff Draper:
Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs. 222-225 - Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev:
A multiword based high speed ECC scheme for low-voltage embedded SRAMS. 226-229 - T. S. Doorn, E. Jan W. ter Maten, J. A. Croon, Alessandro Di Bucchianico
Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield. 230-233 - Mohamed H. Abu-Rahma, Mohab Anis, Sei Seung Yoon:
A robust single supply voltage SRAM read assist technique using selective precharge. 234-237 - Lianming Li, Patrick Reynaert
A 90nm CMOS mm-wave VCO using an LC tank with inductive division. 238-241 - Srdjan Glisic, Yaoming Sun, Frank Herzel, Maxim Piz, Eckhard Grass, Christoph Scheytt, Wolfgang Winkler:
A fully integrated 60 GHz transmitter front-end with a PLL, an image-rejection filter and a PA in SiGe. 242-245 - Hugo Veenstra, Marc Notten:
60GHz quadrature doppler radar transceiver in a 0.25μm SiGe BiCMOS technology. 246-249 - Yikun Yu, Peter G. M. Baltus, Arthur H. M. van Roermund, Dennis Jeurissen, Anton de Graauw, Edwin van der Heijden, Ralf Pijper:
A 60GHz digitally controlled phase shifter in CMOS. 250-253 - Francesco M. De Paola
A 71-73 GHz voltage-controlled standing-wave oscillator in 90 nm CMOS technology. 254-257 - Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara:
On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. 258-261 - Martin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl:
A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS. 262-265 - Luca Picolli, Piero Malcovati
A 90nm 8b 120Ms/s-250Ms/s pipeline ADC. 266-269 - Martin Trojer, Mauro Cleris, Ulrich Gaier, Thomas Hebein, Peter Pridnig, Bernhard Kuttin, Bernhard Tschuden, Christian Krassnitzer, Christian Kuttin, Wolfgang Pribyl:
A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications. 270-273 - Ybe Creten, Patrick Merken, Robert Mertens, Willy Sansen, Chris Van Hoof
An 8-bit Flash Analog-to-Digital Converter in standard CMOS technology functional in ultra wide temperature range from 4.2 K to 300 K. 274-277 - Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability. 278-281 - Mahmut E. Sinangil, Naveen Verma, Anantha P. Chandrakasan:
A reconfigurable 65nm SRAM achieving voltage scalability from 0.25-1.2V and performance scalability from 20kHz-200MHz. 282-285 - Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. 286-289 - Peter Geens, Wim Dehaene:
A dual port dual width 90nm SRAM with guaranteed data retention at minimal standby supply voltage. 290-293 - Thierry Taris, Yann Deval
Current reuse CMOS LNA for UWB applications. 294-297 - Sumit Bagga, Zoubir Irahhauten, Sandro A. P. Haddad, Wouter A. Serdijn, John R. Long, John J. Pekarik:
A UWB transformer-C orthonormal state space band-reject filter in 0.13 μm CMOS. 298-301 - Yunzhi Dong, Yi Zhao, John F. M. Gerrits, Gerrit van Veenendaal, John R. Long:
A 9mW high band FM-UWB receiver front-end. 302-305 - Fabio Sebastiano
A low-voltage mobility-based frequency reference for crystal-less ULP radios. 306-309 - Viola Schaffer, Martijn F. Snoeij, Mikhail V. Ivanov:
A 36V precision programmable gain amplifier with CMRR exceeding 120dB in all gains. 310-313 - Ivonne Di Sancarlo, Dario Giotta, Andrea Baschirotto
A 65-nm 84-dB-gain 200-MHz-UGB CMOS fully-differential three-stage amplifier with a novel Common Mode control. 314-317 - Jean-Michel Redoute
A CMOS source-buffered differential input stage with high EMI suppression. 318-321 - Willem H. Groeneweg:
Analog signal processing for a class D audio amplifier in 65 nm CMOS technology. 322-325 - Domagoj Siprak, Marc Tiebout, Peter Baumgartner:
Reduction of VCO phase noise through forward substrate biasing of switched MOSFETs. 326-329 - Mikko Kaltiokallio, Ville Saari, Tapio Rapinoja, Kari Stadius, Jussi Ryynänen
A WiMedia UWB receiver with a synthesizer. 330-333 - Shengxi Diao, Yuanjin Zheng:
An ultra low power and high efficiency UWB transmitter for WPAN applications. 334-337 - Eun-Chul Park, Inhyo Ryu, Jeongwook Koh, Chun-Deok Suh:
A 3-10 GHz flexible CMOS LO generator for MB-OFDM UWB application using wide tunable VCOs. 338-341 - Shoji Otaka, Masahiro Hosoya, Hiroaki Ishihara, Toru Hashimoto, Yuta Araki:
0.13 μm CMOS Cartesian loop transmitter IC with fast calibration and switching scheme from opened to closed loop. 342-345 - Wim Kruiskamp, Rene Beumer:
Low drop-out voltage regulator with full on-chip capacitance for slot-based operation. 346-349 - Hong-Wei Huang, Chia-Hsiang Lin, Ke-Horng Chen
High-performance low-dropout regulator achieved by fast transient mechanism. 350-353 - Wing Yan Leung, Tsz Yin Man, Mansun Chan
A high-power-LED driver with power-efficient LED-current sensing circuit. 354-357 - Chun-Yu Hsieh, Ke-Horng Chen
Boost DC-DC converter with charge-recycling (CR) and fast reference tracking (FRT) techniques for high-efficiency and low-cost LED driver. 358-361 - Xueyang Geng, Xuefeng Yu, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
An 11-bit 8.6GHz direct digital synthesizer MMIC with 10-bit segmented nonlinear DAC. 362-365 - Stefano Cipriani, Eric Duvivier, Gianni Puccio, Lorenzo Carpineto, Biagio Bisanti, Francesco Coppola, Martin Alderton, Jeremy Goldblatt:
Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction. 366-369 - Jérémie Chabloz, David Ruffieux, Christian C. Enz:
A low-power programmable dynamic frequency divider. 370-373 - Abhijith Arakali, Nema Talebbeydokthi, Srikanth Gondi, Pavan Kumar Hanumolu:
Supply-noise mitigation techniques in phase-locked loops. 374-377 - Nick Van Helleputte
A 46pJ/pulse analog front-end in 130nm CMOS for UWB impulse radio receivers. 378-381 - Prakash E. Thoppay, Catherine Dehollain, Michel J. Declercq:
A 7.5mA 500 MHz UWB receiver based on super-regenerative principle. 382-385 - Yuan Gao
Low-Power CMOS RF front-end for non-coherent IR-UWB receiver. 386-389 - Muhammad Anis, Reinhard Tielert, Norbert Wehn:
Super-regenerative UWB impulse detector with synchronized quenching mechanism. 390-393 - Valentijn De Smedt
A fully-integrated Wienbridge topology for ultra-low-power 86ppm/°C 65nm CMOS 6MHz clock reference with amplitude regulation. 394-397 - Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. 398-401 - Enrico Dallago, Daniele Miatton, Giuseppe Venchi, Valeria Bottarel, Giovanni Frattini, Giulio Ricotti, Monica Schipani:
Electronic interface for Piezoelectric Energy Scavenging System. 402-405 - Anna Richelli
A 0.2V-1.2V converter for power harvesting applications. 406-409 - Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. 410-413 - Maja Vidojkovic, Mihai A. T. Sanduleanu
A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP. 414-417 - Axel Flament, Antoine Frappé
A 1.2 GHz semi-digital reconfigurable FIR bandpass filter with passive power combiner. 418-421 - Ping-Ying Wang, Hsiang-Hui Chang, Jing-Hong Conan Zhan:
A fractional spur reduction technique for RF TDC-based all digital PLLs. 422-425 - Carolynn Bernier
An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications. 426-429 - Marika Tedeschi, Antonio Liscidini
A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer. 430-433 - Dong Han, Yuanjin Zheng:
An ultra low power GFSK demodulator for wireless body area network. 434-437 - Marco Cavallaro, Alessandro Italia, Giuseppina Sapone, Giuseppe Palmisano:
A 3∓5 GHz low-complexity ultra-wideband CMOS RF front-end for low data-rate WPANs. 438-441 - Syed A. Jawed, Davide Cattin, Massimo Gottardi, Nicola Massari, Andrea Baschirotto
A 828μW 1.8V 80dB dynamic-range readout interface for a MEMS capacitive microphone. 442-445 - Paolo Bruschi
A low-power capacitance to pulse width converter for MEMS interfacing. 446-449 - Akram O. Nafee, David A. Johns:
A 14 - bit micro-watt power scalable automotive MEMS pressure sensor interface. 450-453 - Frederic Nabki
A high gain-bandwidth product transimpedance amplifier for MEMS-based oscillators. 454-457 - Mohamad Rahal, Andreas Demosthenous:
A synchronous chopping technique and implementation for high-frequency precision sensing. 458-461 - Kwanho Kim, Joo-Young Kim, Seungjin Lee, Minsu Kim, Hoi-Jun Yoo:
A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip. 462-465 - Torsten Limberg, Markus Winter, Marcel Bimberg, Reimund Klemm, Emil Matús, Marcos B. S. Tavares, Gerhard P. Fettweis, Hendrik Ahlendorf, Pablo Robelly:
A fully programmable 40 GOPS SDR single chip baseband for LTE/WiMAX terminals. 466-469 - Henrik Fredriksson, Christer Svensson:
2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE. 470-473 - Tomoaki Maekawa, Hiroyuki Ito, Kazuya Masu
An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx. 474-477 - Crescenzo D'Alessandro, Alex Bystrov
Implementation of a phase-encoding signalling prototype chip. 478-481 - Calogero D. Presti, Francesco Carrara, Giuseppe Palmisano, Antonino Scuderi:
A high-resolution 24-dBm Digitally-Controlled CMOS PA for multi-Standard RF polar transmitters. 482-485 - Xin He, Manel Collados, Nenad Pavlovic, Jan van Sinderen:
A 1.2V, 17dBm digital polar CMOS PA with transformer-based power interpolating. 486-489 - Po-Chih Wang, Kai-Yi Huang, Yu-Fu Kuo, Ming-Chong Huang, Chao-Hua Lu, Tzung-Ming Chen, Chia-Jun Chang, Ka-Un Chan, Ta-Hsun Yeh, Wen-Shan Wang, Ying-Hsi Lin, Chao-Cheng Lee:
A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process. 490-493 - Angelo Scuderi, Egidio Ragonese
0.13-μm SiGe BiCMOS radio front-end circuits for 24-GHz automotive short-range radar sensors. 494-497 - Yiqun Cao, Marc Tiebout, Vadim Issakov
A 24GHz FMCW radar transmitter in 0.13 μm CMOS. 498-501 - Sebastien Barasinski, Ludovic Camus, Sylvain Clerc:
A 45nm single power supply SRAM supporting low voltage operation down to 0.6V. 502-505
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