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ISSCC 2011: San Francisco, CA, USA
- IEEE International Solid-State Circuits Conference, ISSCC 2011, Digest of Technical Papers, San Francisco, CA, USA, 20-24 February, 2011. IEEE 2011, ISBN 978-1-61284-303-2
Paper Sessions
Plenary Session
- Stephen Oesterle, Paul Gerrish, Peng Cong:
New interfaces to the body through implantable-system integration. 9-14 - Jo De Boeck:
Game-changing opportunities for wireless personal healthcare and lifestyle. 15-21 - Oh-Hyun Kwon:
Eco-friendly semiconductor technologies for healthy living. 22-28 - Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul:
Beyond the horizon: The next 10x reduction in power - Challenges and solutions. 31
Technologies for Health
- Joonsung Bae, Kiseok Song, Hyungwoo Lee, Hyunwoo Cho, Long Yan, Hoi-Jun Yoo:
A 0.24nJ/b wireless body-area-network transceiver with scalable double-FSK modulation. 34-36 - Seulki Lee, Long Yan, Taehwan Roh, Sunjoo Hong, Hoi-Jun Yoo:
A 75μW real-time scalable network controller and a 25μW ExG sensor IC for compact sleep-monitoring applications. 36-38 - Yu-Te Liao
, Huanfen Yao, Babak A. Parviz, Brian P. Otis:
A 3μW wirelessly powered CMOS glucose sensor for an active contact lens. 38-40 - Domenico Zito, Domenico Pepe
A 90nm CMOS SoC UWB pulse radar for respiratory rate monitoring. 40-41 - Franz Schuster, Hadley Videlier, Antoine Dupret, Dominique Coquillat, Maciej Sakowicz
A broadband THz imager in a low-cost CMOS technology. 42-43 - Shuenn-Yuh Lee, Yu-Cheng Su, Ming-Chun Liang, Jia-Hua Hong, Cheng-Han Hsieh, Chung-Min Yang, You-Yin Chen, Hsin-Yi Lai, Jou-Wei Lin, Qiang Fang
A programmable implantable micro-stimulator SoC with wireless telemetry: Application in closed-loop endocardial stimulation for cardiac pacemaker. 44-45 - Yoonmyung Lee
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization. 46-48 - David Ruffieux, Matteo Contaldo, Jacques Haesler, Steve Lecomte:
A low-power fully integrated RF locked loop for Miniature Atomic Clock. 48-50
RF Techniques
- Robert Bogdan Staszewski
Spur-free all-digital PLL in 65nm for mobile phones. 52-54 - Nenad Pavlovic, Jos Bergervoet:
A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL. 54-56 - Chang-Tsung Fu, Hasnain Lakdawala, Stewart S. Taylor, Krishnamurthy Soumyanath:
A 2.5GHz 32nm 0.35mm2 3.5dB NF -5dBm P1dB fully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection. 56-58 - David A. Calvillo-Cortes, Mustafa Acar, Mark P. van der Heijden, Melina Apostolidou, Leo C. N. de Vreede, Domine Leenaerts, Jan Sonsky:
A 65nm CMOS pulse-width-controlled driver with 8Vpp output voltage for switch-mode RF PAs up to 3.6GHz. 58-60 - Ahmad Mirzaei, Hooman Darabi, David Murphy:
A low-power process-scalable superheterodyne receiver with integrated high-Q filters. 60-62 - Jonathan Borremans, Gunjan Mandal, Vito Giannini
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers. 62-64 - Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta
A 1.0-to-4.0GHz 65nm CMOS four-element beamforming receiver using a switched-capacitor vector modulator with approximate sine weighting via charge redistribution. 64-66 - Aslam A. Rafi, Alessandro Piovaccari, Peter J. Vancorenland, Tyson Tuttle:
A harmonic rejection mixer robust to RF device mismatches. 66-68
Enterprise Processors & Components
- James D. Warnock, Y. Chan, William V. Huott, Sean M. Carey, Michael F. Fee, Huajun Wen, Mary Jo Saccamango, Frank Malgioglio, Patrick J. Meaney, Donald W. Plass, Yuen H. Chan, Mark D. Mayo, Guenter Mayer, Leon J. Sigal, David L. Rude, Robert M. Averill III, Michael H. Wood, Thomas Strach, Howard H. Smith, Brian W. Curran, Eric M. Schwarz, Lee Eisen, Doug Malone, Steve Weitzel, Pak-kin Mak, Thomas J. McPherson, Charles F. Webb:
A 5.2GHz microprocessor chip for the IBM zEnterprise™ system. 70-72 - Antonio Pelella, Yuen H. Chan, Bargav Balakrishnan, Pradip Patel, Daniel Rodko, Richard E. Serton:
Dynamic hit logic with embedded 8Kb SRAM in 45nm SOI for the zEnterprise™ processor. 72-73 - Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma, Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayanan:
A 32nm Westmere-EX Xeon® enterprise processor. 74-75 - Weiwu Hu, Ru Wang, Yunji Chen
Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS. 76-78 - Tim C. Fischer, Srikanth Arekapudi, Eric Busta, Carl Dietz, Michael Golden, Scott Hilker, Aaron Horiuchi, Kevin A. Hurd, Dave Johnson, Hugh McIntyre, Samuel Naffziger, James Vinh, Jonathan White, Kathryn Wilcox:
Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. 78-80 - Michael Golden, Srikanth Arekapudi, James Vinh:
40-Entry unified out-of-order scheduler and integer execution unit for the AMD Bulldozer x86-64 core. 80-82 - Shenggao Li
Clock generation for a 32nm server processor with scalable cores. 82-83 - Reid J. Riedlinger, Rohit Bhatia, Larry Biro, William J. Bowhill, Eric S. Fetzer, Paul E. Gronowski, Tom Grutkowski:
A 32nm 3.1 billion transistor 12-wide-issue Itanium® processor for mission-critical servers. 84-86
PLLs
- Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power. 88-90 - Che-Fu Liang, Keng-Jan Hsiao:
An injection-locked ring PLL with self-aligned injection window. 90-92 - Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. 92-94 - Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering. 94-96 - Hyung-Jin Lee, Alexandra M. Kern, Sami Hyvonen, Ian A. Young:
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS. 96-97 - Akihide Sai, Takafumi Yamaji, Tetsuro Itakura:
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. 98-100 - Koji Takinami, Richard Strandberg, Paul C. P. Liang, Gregoìre Le Grand de Mercey, Tony Wong, Mahnaz Hassibi:
A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS. 100-102
Sensors & Energy Harvesting
- Luciano Prandi, Carlo Caminada, Luca Coronato, Gabriele Cazzaniga, Fabio Biganzoli, Riccardo Antonello, Roberto Oboe
A low-power 3-axis digital-output MEMS gyroscope with single drive and multiplexed angular rate readout. 104-106 - Jianfeng Wu, Youngcheol Chae, Caspar P. L. van Vroonhoven, Kofi A. A. Makinwa:
A 50mW CMOS wind sensor with ±4% speed and ±2° direction error. 106-108 - Matthias Kuhl, Pascal Gieschke, Daniel Rossbach, Sascha Alexander Hilzensauer, Patrick Ruther, Oliver Paul, Yiannos Manoli:
A telemetric stress-mapping CMOS chip with 24 FET-based stress sensors for smart orthodontic brackets. 108-110 - Rong Wu, Johan H. Huijsing, Kofi A. A. Makinwa:
A 21b ±40mV range read-out IC for bridge transducers. 110-112 - Frédéric Rothan, Hélène Lhermet, Brice Zongo, Cyril Condemine, Henri Sibuet, Patrick Mas, Miguel Debarnot:
A ±1.5% nonlinearity 0.1-to-100A shunt current sensor based on a 6kV isolated micro-transformer for electrical vehicles and home automation. 112-114 - Bart Dierickx
Indirect X-ray photon-counting image sensor with 27T pixel and 15e-rms accurate threshold. 114-116 - Suat U. Ay:
A 1.32pW/frame•pixel 1.2V CMOS energy-harvesting and imaging (EHI) APS imager. 116-118 - Yifeng Qiu, Chris van Liempd, Bert Op het Veld, Peter G. Blanken, Chris Van Hoof
5μW-to-10mW input power range inductive boost converter for indoor photovoltaic energy harvesting with integrated maximum power point tracking algorithm. 118-120 - Ethem Erkan Aktakka, Rebecca L. Peterson
A self-supplied inertial piezoelectric energy harvester with power-management IC. 120-121
Multimedia & Mobile
- Pei-Kuei Tsung, Pin-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang, Hsin-Jung Yang, Shao-Yi Chien
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications. 124-126 - Vivienne Sze, Anantha P. Chandrakasan:
A highly parallel and scalable CABAC decoder for next generation video coding. 126-128 - Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim, Jun-Seok Park, Lee-Sup Kim:
A 275mW heterogeneous multimedia processor for IC-stacking on Si-interposer. 128-130 - Jinwook Oh, Junyoung Park, Gyeonghoon Kim, Seungjin Lee, Hoi-Jun Yoo:
A 57mW embedded mixed-mode neuro-fuzzy accelerator for intelligent multi-core processor. 130-132 - Gordon Gammie, Nathan Ickes, Mahmut E. Sinangil, Rahul Rithe, Jie Gu, Alice Wang, Hugh Mair, Satyendra Datla, Bing Rong, Sushma Honnavara Prasad, Lam Ho, Greg Baldwin, Dennis Buss, Anantha P. Chandrakasan, Uming Ko:
A 28nm 0.6V low-power DSP for mobile applications. 132-134 - Gene C. H. Chuang, Pangan Ting, Jen-Yuan Hsu, Jiun-You Lai, Shun-Chang Lo, Ying-Chuan Hsiao, Tzi-Dar Chiueh:
A MIMO WiMAX SoC in 90nm CMOS for 300km/h mobility. 134-136 - Jyh-Shin Pan, Ming-Yang Chao, Eric Yeh, Wen-Wei Yang, Ching-Wen Hsueh, Shyuan Liao, Jian-Bang Lin, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chia-Hua Chou, Min Chen, Den-Kai Juang, Jen-Hao Yeh, Chieh-Wei Liao, Po-Hung Chen, Kaipon Kao, Chia-Hsin Wu, Wen-Tso Huang, Shih-Hsien Liao, Chih-Heng Shih, Chien-Hsun Tung, Yen-Po Lee:
A 70Mb/s -100.5dBm sensitivity 65nm LP MIMO chipset for WiMAX portable router. 136-138 - Alan N. Willson Jr., Mukund Ojha, Shilpa Agarwal, Thriven Lai, Tzu-Chieh Kuo:
A direct digital frequency synthesizer with minimized tuning latency of 12ns. 138-140
Architectures & Circuits for Next-Generation Wireline Transceivers
- Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. 142-144 - Gaurav Chandra, Moshe Malkin:
A full-duplex 10GBase-T transmitter hybrid with SFDR >65dBc Over 1 to 400MHz in 40nm CMOS. 144-146 - Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee:
A 40Gb/s TX and RX chip set in 65nm CMOS. 146-148 - Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura:
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. 148-150 - Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Satoru Shinke, Masahiro Uno, Kenji Komori, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri
A 12.5+12.5Gb/s full-duplex plastic waveguide interconnect. 150-152 - Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu:
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. 152-154 - Behrooz Abiri, Ravi Shivnaraine, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A 1-to-6Gb/s phase-interpolator-based burst-mode CDR in 65nm CMOS. 154-156 - Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli
A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. 156-158
Wireless & mm-Wave Connectivity
- Kenichi Okada, Kota Matsushita, Keigo Bunsen
A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. 160-162 - Alexandre Siligaris, Olivier Richard, Baudouin Martineau
A 65nm CMOS fully integrated transceiver module for 60GHz wireless HD applications. 162-164 - Sohrab Emami, Robert F. Wiser, Ershad Ali, Mark G. Forbes, Michael Q. Gordon, Xiang Guan, Steve Lo, Patrick T. McElwee, James Parker, Jon R. Tani, Jeffrey M. Gilbert, Chinh H. Doan:
A 60GHz CMOS phased-array transceiver pair for multi-Gb/s wireless communications. 164-166 - Maryam Tabesh, Jiashu Chen, Cristian Marcu, Lingkai Kong, Shinwon Kang, Elad Alon, Ali M. Niknejad:
A 65nm CMOS 4-element Sub-34mW/element 60GHz phased-array transceiver. 166-168 - Shih-Jou Huang, Yu-Ching Yeh, Huaide Wang, Pang-Ning Chen, Jri Lee:
An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS. 168-170 - Shahram Abdollahi-Alibeik, David Weber, Hakan Dogan, William W. Si, Burcin Baytekin, Abbas Komijani, Richard Chang, Babak Vakili-Amini, MeeLan Lee, Haitao Gan, Yashar Rajavi, Hirad Samavati, Brian J. Kaczynski, Sang-Min Lee, Sotirios Limotyrakis, Hyunsik Park, Phoebe Chen, Paul Park, Mike Shuo-Wei Chen, Andrew Chang, Yangjin Oh, Jerry Jian-Ming Yang, Eric Chien-Chih Lin, Lalitkumar Nathawad, Keith Onodera, Manolis Terrovitis, Sunetra Mendis, Kai Shi, Srenik S. Mehta, Masoud Zargari, David K. Su:
A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC. 170-172 - Pui-In Mak
A 0.46mm2 4dB-NF unified receiver front-end for full-band mobile TV in 65nm CMOS. 172-174 - Hiroyuki Kobayashi, Shouhei Kousai, Yoshiaki Yoshihara, Mototsugu Hamada:
An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS. 174-176 - Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho:
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. 176-178
Nyquist-Rate Converters
- Konstantinos Doris, Erwin Janssen, Claudio Nani, Athon Zanikopoulos, Gerard van der Weide:
A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist. 180-182 - Robert Payne, Charles K. Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal:
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. 182-184 - Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. 184-186 - Janet Brunsilius, Eric Siragusa, Steve Kosic, Frank Murden, Ege Yetis, Binh Luu, Jeff Bray, Phil Brown, Allen Barlow:
A 16b 80MS/s 100mW 77.6dB SNR CMOS pipeline ADC. 186-188 - He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. 188-190 - Marcus Yip, Anantha P. Chandrakasan:
A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC. 190-192 - Wei-Hsin Tseng, Chi-Wei Fan, Jieh-Tsorng Wu:
A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz. 192-194 - Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan:
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. 194-196
Non-Volatile Memory Solutions
- Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Toshiaki Edahiro, Takeshi Ogawa, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Hiromitsu Komai, Yuka Furuta, Mai Muramoto, Rieko Tanaka, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara:
A 151mm2 64Gb MLC NAND flash memory in 24nm CMOS technology. 198-199 - Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. 200-202 - Tae-yun Kim, Sang-Don Lee, Jin-su Park, Ho-youb Cho, Byoung-sung You, Kwang-ho Baek, Jae-ho Lee, Chang-won Yang, Misun Yun, Min-su Kim, Jongwoo Kim, Eun-seong Jang, Hyun Chung, Sang-o Lim, Bong-Seok Han, Yo-Hwan Koh:
A 32Gb MLC NAND flash memory with Vth margin-expanding schemes in 26nm CMOS. 202-204 - Shuhei Tanakamaru, Chinglin Hung, Atsushi Esumi, Mitsuyoshi Ito, Kai Li, Ken Takeuchi:
95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm. 204-206 - Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi
An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. 206-208 - Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan:
A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS. 208-210 - Wataru Otsuka, Koji Miyata, Makoto Kitagawa, Keiichi Tsutsui, Tomohito Tsushima, Hiroshi Yoshihara, Tomohiro Namise, Yasuhiro Terao, Kentaro Ogata:
A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput. 210-211 - Ki-Tae Park, Ohsuk Kwon, Sangyong Yoon, Myung-Hoon Choi, In-Mo Kim, Bo-Geun Kim, Min-Seok Kim, Yoon-Hee Choi, Seung-Hwan Shin, Youngson Song, Joo-Yong Park, Jae-Eun Lee, Chang-Gyu Eun, Ho-Chul Lee, Hyeong-Jun Kim, Jun-Hee Lee, Jong-Young Kim, Tae-Min Kweon, Hyun-Jun Yoon, Taehyun Kim, Dong-Kyo Shim, Jongsun Sel, Ji-Yeon Shin, Pansuk Kwak, Jin-Man Han, Keon-Soo Kim, Sungsoo Lee, Youngho Lim, Tae-Sung Jung:
A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology. 212-213
Design in Emerging Technologies
- Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai:
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. 216-218 - Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier. 218-220 - Shingo Takahashi, Nobuhide Yoshida, Kenichi Maruhashi, Muneo Fukaishi:
Real-time current-waveform sensor with plugless energy harvesting from AC power lines for home/building energy-management systems. 220-222 - Alexander V. Rylyakov, Clint Schow, Benjamin G. Lee, William M. J. Green, Joris Van Campenhout, Min Yang, Fuad E. Doany, Solomon Assefa, Christopher V. Jahnes, Jeffrey A. Kash, Yurii A. Vlasov:
A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver. 222-224 - Erik Öjefors, Janus Grzyb, Yan Zhao, Bernd Heinemann, Bernd Tillack, Ullrich R. Pfeiffer
A 820GHz SiGe chipset for terahertz active imaging applications. 224-226 - Hiroaki Ishihara, Toshiyuki Umeda, Katsuya Ohno, Shigeyasu Iwata, Fumi Moritsuka, Tetsuro Itakura, Manabu Ishibe, Keijiro Hijikata, Yasunori Maki:
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller. 226-228 - Makoto Miyamura, Shogo Nakaya, Munehiro Tada
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. 228-229 - Andrzej Radecki, Hayun Chung, Yoichi Yoshida, Noriyuki Miura, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda:
6W/25mm2 inductive power transfer for non-contact wafer-level testing. 230-232 - Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis:
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity. 232-234
Analog Techniques
- Jong Tae Hwang, Kunhee Cho, Donghwan Kim, Minho Jung, Gyehyun Cho, Seunguk Yang:
A simple LED lamp driver IC with intelligent power-factor correction. 236-238 - Sachin Rao, Qadeer Khan, Sarvesh Bang, Damian Swank, Arun Rao, William McIntyre, Pavan Kumar Hanumolu:
A 1.2A buck-boost LED driver with 13% efficiency improvement using error-averaged SenseFET-based current sensing. 238-240 - Mykhaylo A. Teplechuk, Tony Gribben, Christophe Amadi:
Filterless integrated class-D audio amplifier achieving 0.0012% THD+N and 96dB PSRR when supplying 1.2W. 240-242 - Yoshinori Kusuda
A 5.9nV/√Hz chopper operational amplifier with 0.78μV maximum offset and 28.3nV/°C offset drift. 242-244 - Rong Wu, Johan H. Huijsing, Kofi A. A. Makinwa:
A current-feedback instrumentation amplifier with a gain error reduction loop and 0.06% untrimmed gain error. 244-246 - Chinwuba D. Ezekwe, Johan P. Vanderhaegen, Xinyu Xing, Ganesh K. Balachandran:
A 6.7nV/√Hz Sub-mHz-1/f-corner 14b analog-to-digital interface for rail-to-rail precision voltage sensing. 246-248 - Martijn F. Snoeij, Mikhail V. Ivanov:
A 36V JFET-input bipolar operational amplifier with 1μV/°C maximum offset drift and -126dB total harmonic distortion. 248-250 - Gwilym F. Luff:
13.8A 3.3V-supply 120mW differential ADC driver amplifier in 0.18μm SiGe BiCMOS with 108dBc IM3 at 100MHz. 250-252
High-Performance Embedded Memory
- Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens:
A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. 254-256 - Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang:
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. 256-258 - Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu:
An 8MB level-3 cache in 32nm SOI with column-select aliasing. 258-260 - Mahmut E. Sinangil, Hugh Mair, Anantha P. Chandrakasan:
A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6V. 260-262
High-Performance SoCs & Components
- Marcelo Yuffe, Ernest Knoll, Moty Mehalel, Joseph Shor, Tsvika Kurts:
A fully integrated multi-CPU, GPU and memory controller 32nm processor. 264-266 - Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. 266-268 - Wonyoung Kim, David M. Brooks, Gu-Yeon Wei:
A fully-integrated 3-level DC/DC converter for nanosecond-scale DVS with fast shunt regulation. 268-270 - Srinivasa Rao Gutta, Denis Foley, Ajay Naini, Robert Wasmuth, Don Cherepacha:
A low-power integrated x86-64 and graphics processor for mobile computing devices. 270-272 - Dong Jiao, Chris H. Kim:
A programmable adaptive phase-shifting PLL for clock data compensation under resonant supply noise. 272-274 - Marion Doulcier-Verdier, Jean-Max Dutertre
A side-channel and fault-attack resistant AES circuit working on duplicated complemented values. 274-276
mm-Wave Design Techniques
- Juan F. Osorio, Cicero S. Vaucher, Bill Huff, Edwin van der Heijden, Anton de Graauw:
A 21.7-to-27.8GHz 2.6-degrees-rms 40Mw frequency synthesizer in 45nm CMOS for mm-Wave communication applications. 278-280 - Ugo Decanis, Andrea Ghilioni, Enrico Monaco, Andrea Mazzanti, Francesco Svelto:
A mm-Wave quadrature VCO based on magnetically coupled resonators. 280-282 - Andrea Ghilioni, Ugo Decanis, Enrico Monaco, Andrea Mazzanti, Francesco Svelto:
A 6.5mW inductorless CMOS frequency divider-by-4 operating up to 70GHz. 282-284 - Kuo-Ken Huang, David D. Wentzloff:
A 60GHz antenna-referenced frequency-locked loop in 0.13μm CMOS for wireless sensor networks. 284-286 - Omeed Momeni, Ehsan Afshari:
A 220-to-275GHz traveling-wave frequency doubler with -6.6dBm Power at 244GHz in 65nm CMOS. 286-288 - Kaushik Sengupta
Distributed active radiation for THz signal generation. 288-289 - Noël Deferm, Patrick Reynaert
A 120GHz 10Gb/s phase-modulating transmitter in 65nm LP CMOS. 290-292 - Hiroki Sakurai, Yuka Kobayashi, Toshiya Mitomo, Osamu Watanabe, Shoji Otaka:
A 1.5GHz-modulation-range 10ms-modulation-period 180kHzrms-frequency-error 26MHz-reference mixed-mode FMCW synthesizer for mm-wave radar application. 292-294 - Ta-Shun Chu, Jonathan Roderick, SangHyun Chang, Timothy Mercer, Chenliang Du, Hossein Hashemi:
A short-range UWB impulse-radio CMOS sensor for human feature detection. 294-296 - Adrian Tang, Mau-Chung Frank Chang
183GHz 13.5mW/pixel CMOS regenerative receiver for mm-wave imaging applications. 296-298
Biomedical & Displays
- Jiawei Xu, Refet Firat Yazicioglu, Pieter Harpe, Kofi A. A. Makinwa, Chris Van Hoof
A 160μW 8-channel active electrode system for EEG monitoring. 300-302 - Rikky Muller, Simone Gambini, Jan M. Rabaey:
A 0.013mm2 5μW DC-coupled neural signal acquisition IC with 0.5V supply. 302-304 - Steffen Lange, Hongcheng Xu, Christian Lang, Holger Pless, Joachim Becker, Hans-Jürgen Tiedkte, Eckhard Hennig, Maurits Ortmanns:
An AC-powered optical receiver consuming 270μW for transcutaneous 2Mb/s data transfer. 304-306 - Kriangkrai Sooksood
A neural stimulator front-end with arbitrary pulse shape, HV compliance and adaptive supply requiring 0.05mm2 in 0.35μm HVCMOS. 306-308 - Roxana T. Heitz, David B. Barkin, Thomas D. O'Sullivan
A low noise current readout architecture for fluorescence detection in living subjects. 308-310 - Gregory K. Chen, Hassan Ghaed, Razi-Ul Haque
A cubic-millimeter energy-autonomous wireless intraocular pressure monitor. 310-312 - Chockalingam Veerappan, Justin A. Richardson, Richard Walker
A 160×128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter. 312-314 - Bernd Richter, Uwe Vogel, Rigo Herold, Karsten Fehse
Bidirectional OLED microdisplay: Combining display and image sensor functionality into a monolithic CMOS chip. 314-316 - Hyunsik Kim
A 0.014mm2 9b switched-current DAC for AMOLED mobile display drivers. 316-318 - Chih-Wen Lu, Ping-Yeh Yin, Ching-Min Hsiao, Mau-Chung Frank Chang
A 10b resistor-resistor-string DAC with current compensation for compact LCD driver ICs. 318-320
Organic Innovations
- Kris Myny
An 8b organic microprocessor on plastic foil. 322-324 - Tarek Zaki, Frederik Ante, Ute Zschieschang, Joerg Butschke, Florian Letzkus, Harald Richter, Hagen Klauk, Joachim N. Burghartz:
A 3.3V 6b 100kS/s current-steering D/A converter using organic thin-film transistors on glass. 324-325 - Wei Zhang, Mingjing Ha, Daniele Braga
A 1V printed organic DRAM cell based on ion-gel gated transistors with a sub-10nW-per-cell Refresh Power. 326-328 - Anis Daami, Cécile Bory, Mohamed Benwadih
Fully printed organic CMOS technology on plastic substrates for digital and analog applications. 328-330
Low-Power Digital Techniques
- Maryam Ashouei, Jos Hulzink, Mario Konijnenburg, Jun Zhou, Filipa Duarte, Arjan Breeschoten, Jos Huisken, Jan Stuyt, Harmke de Groot, Francisco Barat, Johan David, Johan Van Ginderdeuren:
A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V. 332-334 - Michael Zwerg, Adolf Baumann, Rüdiger Kuhn, Matthias Arnold, Ronald Nerlich, Marcus Herzog, Ralph Ledwa, Christian Sichert, Volker Rzehak, Priya Thanigai, Björn Oliver Eversmann:
An 82μA/MHz microcontroller with embedded FeRAM for energy-harvesting applications. 334-336 - Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard:
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. 336-337 - Chen Kong Teh, Tetsuya Fujita, Hiroyuki Hara, Mototsugu Hamada:
A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS. 338-340 - Niklas Lotze, Yiannos Manoli:
A 62mV 0.13μm CMOS standard-cell-based design technique using schmitt-trigger logic. 340-342 - Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David T. Blaauw, Dennis Sylvester:
A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining. 342-344
High-Speed Transceivers & Building Blocks
- Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Takashi Miyoshi, Hideki Osone, Samir Parikh, Subodh M. Reddy, Toshiyuki Shibuya, Yasushi Umezawa, William W. Walker:
A 4-channel 10.3Gb/s transceiver with adaptive phase equalizer for 4-to-41dB loss PCB channel. 346-348 - Shaolei Quan, Freeman Zhong, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang:
A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS. 348-350 - Andrew K. Joy, Hugh Mair, Hae-Chang Lee, Arnold Feldman, Clemenz L. Portmann, Neil Bulman, Eugenia Cordero Crespo, Peter Hearne, Patty Huang, Ben Kerr, Pulkit Khandelwal, Franz Kuhlmann, Shaun Lytollis, Joaquim Machado, Casey Morrison, Scott Morrison, Shahriar Rabii, Dushmantha Rajapaksha, Vishnu Ravinuthula, Giuseppe Surace:
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver. 350-351 - Mehrdad Ramezani, Mohamed Abdalla, Ayal Shoval, Marcus van Ierssel, Afshin Rezayee, Angus McLaren, Chris D. Holdenried, Jennifer Pham, Eric So, David Cassan, Saman Sadr:
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology. 352-354 - Shayan Shahramian, Clifford Ting, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A pattern-guided adaptive equalizer in 65nm CMOS. 354-356 - Yi-Chieh Huang, Shen-Iuan Liu:
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization. 356-358 - Wang-Soo Kim, Chang-Kyung Seong, Woo-Young Choi:
A 5.4Gb/s adaptive equalizer using asynchronous-sampling histograms. 358-359 - Sewook Hwang, Minyoung Song
A 0.076mm2 3.5GHz spread-spectrum clock generator with memoryless Newton-Raphson modulation profile in 0.13μm CMOS. 360-362
Cellular
- Ivan Siu-Chuang Lu, Chi-Yao Yu, Yen-Horng Chen, Lan-chou Cho, Chih-hao Eric Sun, Chih-Chun Tang, George Chien:
A SAW-less GSM/GPRS/EDGE receiver embedded in a 65nm CMOS SoC. 364-366 - Magnus Nilsson, Sven Mattisson, Nikolaus Klemmer, Martin Anderson, Torkel Arnborg, Peter Caputa, Staffan Ek, Lin Fan, Henrik Fredriksson, Fabien Garrigues, Henrik Geis, Hans Hagberg, Joel Hedestig, Hu Huang, Yevgeniy Kagan, Niklas Karlsson, Henrik Kinzel, Thomas Mattsson, Thomas Mills, Fenghao Mu, Andreas Mårtensson, Lars Nicklasson, Filip Oredsson, Ufuk Ozdemir, Fitzgerald Park, Tony Pettersson, Tony Påhlsson, Markus Pålsson, Stephane Ramon, Magnus Sandgren, Per Sandrup, Anna-Karin Stenman, Roland Strandberg, Lars Sundström
A 9-band WCDMA/EDGE transceiver supporting HSPA evolution. 366-368 - Alberto Cicalini, Sankaran Aniruddhan, Rahul Apte, Frederic Bossu, Ojas Choksi, Dan Filipovic, Kunal Godbole, Tsai-Pi Hung, Christos Komninakis, David Maldonado, Chiewcharn Narathong, Babak Nejati, Deirdre O'Shea, Xiaohong Quan, Raj Rangarajan, Janakiram Sankaranarayanan, Andrew See, Ravi Sridhara, Bo Sun, Wenjun Su, Klaas van Zalinge, Gang Zhang, Kamal Sahota:
A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor. 368-370 - Federico Beffa, Tze Yee Sin, Alexander Tanzil, David Ivory, Bernard Tenbroek, Jon Strange, Walid Ali-Ahmad:
A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOS. 370-372 - Xin He, Harish Kundur:
A compact SAW-less multiband WCDMA/GPS receiver front-end with translational loop for input matching. 372-374 - Vito Giannini
A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS. 374-376 - Zdravko Boos, Andreas Menkhoff, Franz Kuttner, Markus Schimper, José Moreira, Hans Geltinger, Timo Gossmann, Peter Pfann, Alexander Belitzer, Thomas Bauernfeind:
A fully digital multimode polar transmitter employing 17b RF DAC in 3G mode. 376-378 - Michael Youssef, Alireza Zolfaghari, Hooman Darabi, Asad A. Abidi:
A low-power wideband polar transmitter for 3G applications. 378-380
DC/DC Converters
- Arnold James D'Souza, Ravpreet Singh, J. Raja Prabhu, Gajendranath Chowdary
A fully integrated power-management solution for a 65nm CMOS cellular handset chip. 382-384 - Franz Kuttner, Harun Habibovic, Thomas Hartig, Michael Fulde, Gernot Babin, Andreas Santner, Peter Bogner, Claus Kropf, Harald Riesslegger, Uwe Hodel:
A digitally controlled DC-DC converter for SoC in 28nm CMOS. 384-385 - Saurav Bandyopadhyay, Yogesh K. Ramadass, Anantha P. Chandrakasan:
20μA to 100mA DC-DC converter with 2.8 to 4.2V battery supply for portable applications in 45nm CMOS. 386-388 - Tao Liu, Hyunsoo Yeom, Bert Vermeire, Philippe Adell, Bertan Bakkaloglu
A digitally controlled DC-DC buck converter with lossless load-current sensing and BIST functionality. 388-390 - Tae-Hwang Kong, Young-Jin Woo, Se-Won Wang, Sung-Wan Hong, Gyu-Hyeong Cho:
Zero-order control of boost DC-DC converter with transient enhancement using residual current. 390-392 - Sungwoo Lee, Seungchul Jung, Jin Huh, Changbyung Park, Chun-Taek Rim, Gyu-Hyeong Cho:
Robust and efficient synchronous buck converter with near-optimal dead-time control. 392-394 - Weiwei Xu, Ye Li, Zhiliang Hong, Dirk Killat:
A 90% peak efficiency single-inductor dual-output buck-boost converter with extended-PWM control. 394-396 - Chengwu Tao, Ayman A. Fayed
Spurious-noise-free buck regulator for direct powering of analog/RF loads using PWM control with random frequency hopping and random phase chopping. 396-398
Image Sensors
- Min-Woong Seo, Sungho Suh, Tetsuya Iida, Hiroshi Watanabe, Taishi Takasawa, Tomoyuki Akahori, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Shoji Kawahito:
An 80μVrms-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC. 400-402 - Christian Lotto, Peter Seitz, Thomas Baechler:
A sub-electron readout noise CMOS image sensor with pixel-level open-loop voltage amplification. 402-404 - Takeharu G. Etoh, Dung H. Nguyen, Son Vu Truong Dao
A 16 Mfps 165kpixel backside-illuminated CCD. 406-408 - Yuichiro Yamashita, Hidekazu Takahashi, Shin Kikuchi, Keisuke Ota, Masato Fujita, Satoshi Hirayama, Taikan Kanou, Sakae Hashimoto, Genzo Momma, Shunsuke Inoue:
A 300mm wafer-size CMOS image sensor with in-pixel voltage-gain amplifier and column-level differential readout circuitry. 408-410 - Richard J. Walker
A 128×96 pixel event-driven phase-domain ΔΣ-based fully digital 3D camera in 0.13μm CMOS imaging technology. 410-412 - Albert Wang, Patrick R. Gill, Alyosha C. Molnar:
An angle-sensitive CMOS imager for single-sensor 3D photography. 412-414 - Robert Johansson
A 1/13-inch 30fps VGA SoC CMOS image sensor with shared reset and transfer-gate pixel control. 414-415 - Sangjoo Lee, Kyungho Lee, Jongeun Park, Hyungjun Han, Younghwan Park, Taesub Jung, Youngheup Jang, Bumsuk Kim, Yitae Kim, Shay Hamami, Uzi Hizi, Mickey Bahar, Changrok Moon, JungChak Ahn, Duckhyung Lee, Hiroshige Goto, Yun-Tae Lee:
A 1/2.33-inch 14.6M 1.4μm-pixel backside-illuminated CMOS image sensor with floating diffusion boosting. 416-418 - Dan Pates, Jeong-Ho Lyu, Shinji Osawa, Isao Takayanagi, Toshiaki Sato, Tim Bales, Katsuyuki Kawamura, Eduard Pages, Shinichiro Matsuo, Tetsuji Kawaguchi, Tadashi Sugiki, Norio Yoshimura, Junichi Nakamura, John Ladd, Zhiping Yin, Russell Iimura, Xiaofeng Fan, Scott Johnson, Aditya Rayankula, Rick Mauritzson, Gennadiy Agranov:
An APS-C format 14b digital CMOS image sensor with a dynamic response pixel. 418-420 - Takayuki Toyama, Koji Mishina, Koji Tsuchiya, Tatsuya Ichikawa, Hiroyuki Iwaki, Yuji Gendai
A 17.7Mpixel 120fps CMOS image sensor with 34.8Gb/s readout. 420-422
Transmitter Blocks
- Emanuele Lopelli, Silvian Spiridon, Johan van der Tang:
A 40nm wideband direct-conversion transmitter with sub-sampling-based output power, LO feedthrough and I/Q imbalance calibration. 424-426 - Yulin Tan, Hongtao Xu, Mohammed A. El-Tanani
A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS. 426-428 - Sang-Min Yoo, Jeffrey S. Walling
A switched-capacitor power amplifier for EER/polar transmitters. 428-430 - Woonyun Kim, Ki Seok Yang, Jeonghu Han, Jaejoon Chang, Chang-Ho Lee:
An EDGE/GSM quad-band CMOS power amplifier. 430-432 - Jiashu Chen, Ali M. Niknejad:
A compact 1V 18.6dBm 60GHz power amplifier in 65nm CMOS. 432-433
CDRs & Equalization Techniques
- Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune:
A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. 436-438 - Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. 438-450 - Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu:
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. 440-442 - Hui Pan
A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS. 442-444 - Yu-Ming Ying, Shen-Iuan Liu:
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. 444-446 - Meisam Honarvar Nazari, Azita Emami-Neyestanak
A 15Gb/s 0.5mW/Gb/s 2-tap DFE receiver with far-end crosstalk cancellation. 446-448 - Halil Cirit, Marc J. Loinaz:
A 10Gb/s half-UI IIR-tap transmitter in 40nm CMOS. 448-450 - Sungchun Jang, Heesoo Song, Seokmin Ye, Deog-Kyoon Jeong:
A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit. 450-452
Low-Power Wireless
- Hannes Reinisch, Martin Wiessflecker, Stefan Gruber, Hartwig Unterassinger, Günter Hofer, Michael Klamminger, Wolfgang Pribyl, Gerald Holweg:
A 7.9μW remotely powered addressed sensor node using EPC HF and UHF RFID technology with -10.3dBm sensitivity. 454-456 - Eun-Hee Kim, Kwyro Lee, Jinho Ko:
An isolator-less CMOS RF front-end for UHF mobile RFID reader. 456-458 - Maja Vidojkovic, Xiongchuan Huang, Pieter Harpe, Simonetta Rampu, Cui Zhou, Li Huang, Koji Imamura, Ben Busze, Frank Bouwens, Mario Konijnenburg, Juan Santana, Arjan Breeschoten, Jos Huisken
A 2.4GHz ULP OOK single-chip transceiver for healthcare applications. 458-460 - Jagdish Nayayan Pandey, Jianlei Shi, Brian P. Otis:
A 120μW MICS/ISM-band FSK receiver with a 44μW low-power mode based on injection-locking and 9x frequency multiplication. 460-462 - Chia-Hsin Wu, Wen-Chieh Tsai, Chun-Geik Tan, Chun-Nan Chen, Kuan-I Li, Jui-Lin Hsu, Chi-Lun Lo, Hsin-Hua Chen, Sheng-Yuan Su, Kun-Tso Chen, Min Chen, Osama Shana'a
A GPS/Galileo SoC with adaptive in-band blocker cancellation in 65nm CMOS. 462-464 - Sujiang Rong, Howard C. Luong
A 0.05-to-10GHz 19-to-22GHz and 38-to-44GHz SDR frequency synthesizer in 0.13μm CMOS. 464-466 - Tamer A. Ali, Amr Amin Hafez, Robert J. Drost, Ronald Ho, Chih-Kong Ken Yang:
A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning. 466-468
Oversampling Converters
- Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, Kofi A. A. Makinwa:
A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW. 470-472 - John G. Kauffman, Pascal Witte
An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization. 472-474 - Nima Maghari, Un-Ku Moon:
A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer. 474-476 - Fridolin Michel, Michiel Steyaert
A 250mV 7.5μW 61dB SNDR CMOS SC ΔΣ modulator using a near-threshold-voltage-biased CMOS inverter technique. 476-478 - Aldo Pena-Perez, Edoardo Bonizzoni, Franco Maloberti:
A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW. 478-480 - Ying Cao, Paul Leroux
A 1.7mW 11b 1-1-1 MASH ΔΣ time-to-digital converter. 480-482 - Abhishek Bandyopadhyay, Michael Determan, Sejun Kim, Khiem Nguyen:
A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC. 482-483 - Lars Risbo, Rahmi Hezar, Burak Kelleci, Halil Kiper, Mounir Fares:
A 108dB-DR 120dB-THD and 0.5Vrms output audio DAC with inter-symbol-interference-shaping algorithm in 45nm CMOS. 484-485
DRAM & High-Speed I/O
- Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. 488-490 - Noriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda:
A 2.7Gb/s/mm2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stacking. 490-492 - Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda:
A 12Gb/s non-contact interface with coupled transmission lines. 492-494 - Woo-Yeol Shin, Gi-Moon Hong, Hyongmin Lee, Jaeduk Han, Sunkwon Kim, Kyu-Sang Park
A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. 494-496 - Jung-Sik Kim, Chi Sung Oh, Hocheol Lee, Donghyuk Lee, Hyong-Ryol Hwang, Sooman Hwang, Byongwook Na, Joungwook Moon, Jin-Guk Kim, Hanna Park, Jang-Woo Ryu, Kiwon Park, Sang-Kyu Kang, So-Young Kim, Hoyoung Kim, Jong-Min Bang, Hyunyoon Cho, Minsoo Jang, Cheolmin Han, Jung-Bae Lee, Kyehyun Kyung, Joo-Sun Choi, Young-Hyun Jun:
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. 496-498 - Seung-Jun Bae, Young-Soo Sohn, Tae-Young Oh, Si-Hong Kim, Yun-Seok Yang, Dae-Hyun Kim
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. 498-500 - Hoeju Chung, Byung-Hoon Jeong, ByungJun Min, Youngdon Choi, Beak-Hyung Cho, Junho Shin, Jinyoung Kim, Jung Sunwoo, Joon-min Park, Qi Wang, Yong-jun Lee, Sooho Cha, Dukmin Kwon, Sang-Tae Kim, Sunghoon Kim
A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. 500-502 - Hyun-Woo Lee, Ki-Han Kim, Young-Kyoung Choi, Ju-Hwan Shon, Nak-Kyu Park, Kwan-Weon Kim, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung:
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. 502-504 - Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii:
An embedded DRAM technology for high-performance NAND flash memories. 504-505 - Ki Chul Chun, Wei Zhang, Pulkit Jain, Chris H. Kim:
A 700MHz 2T1C embedded DRAM macro in a generic logic process with no boosted supplies. 506-507
FORUMS
- Gabriele Manganaro, Domine Leenaerts, Francesco Dantoni, Andrea Baschirotto, Robert Bogdan Staszewski
Advanced transmitters for wireless infrastructure. 512-513 - Ken Takeuchi, Ken Chang, Kevin Zhang, Tadaaki Yamauchi, Roberto Gastaldi:
Ultra-low voltage VLSIs for energy efficient systems. 514-515 - Christian C. Enz, Andreia Cathelin, Maysam Ghovanloo, Stefan Heinen, Minkyu Je, David Scott:
Towards personalized medicine and monitoring for healthy living. 516-517 - Tobias Noll, Raney Southerland, Vladimir Stojanovic, Sonia Leon, Lew Chua-Eoan, Alice Wang, Byeong-Gyu Nam, Masaya Sumita:
Design of "green" high-performance processor circuits. 518-519 - Johannes Solhusvik, Albert Theuwissen, Sam Kavusi, Tetsuo Nomoto, Iliana Chen:
Image sensors for 3D capture. 520-521 - Ali Sheikholeslami, Franz Dielacher
High-speed transceivers: Standards, challenges, and future. 522-523
Short Course
- John R. Long, Hooman Darabi, Frank Op't Eynde, Behzad Razavi, Robert Bogdan Staszewski
Cellular and wireless LAN transceivers: From systems to circuit design. 524
Evening Sessions
- Jerry Lin, Franz Dielacher
Good, bad, ugly - 20 years of broadband evolution: What's next? 525 - Don Draper:
20-22nm technology options and design implications. 526 - Boris Murmann, Venu Gopinathan:
Data converter breakthroughs in retrospect. 528 - Pascal Urard, Jun Ohta:
Wireless sensor systems: Solution & technology. 529 - Nicky Lu, Leland Chang, Daisaburo Takashima:
Future system and memory architectures: Transformations by technology and applications. 530 - Hoi-Jun Yoo, Alison J. Burdett:
Body area network: Technology, solutions, and standardization. 531 - Didier Belot, George Chien:
Gb/s+ portable wireless communications. 532 - Jed Hurwitz, Wing-Hung Ki
Technologies for smart grid and smart meter. 533
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