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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 35
Volume 35, Number 1, January 2016
- Xuanyao Fong
, Yusung Kim
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives. 1-22 - Jun Tao, Changhai Liao, Xuan Zeng, Xin Li:
Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits. 23-36 - Yu Zheng, Shuo Yang, Swarup Bhunia
SeMIA: Self-Similarity-Based IC Integrity Analysis. 37-48 - Chongxi Bao, Domenic Forte
On Reverse Engineering-Based Hardware Trojan Detection. 49-57 - Liang Shi, Kaijie Wu
Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems. 58-71 - Amit Kumar Singh, Muhammad Shafique
Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs. 72-85 - Philipp Niemann, Robert Wille
QMDDs: Efficient Quantum Function Representation and Manipulation. 86-99 - Adrian Alin Lifa, Petru Eles, Zebo Peng:
A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching. 100-113 - Dimitri Kagaris:
MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool. 114-127 - Shyamapada Mukherjee, Suchismita Roy:
Nearly-2-SAT Solutions for Segmented-Channel Routing. 128-140 - Baris Arslan, Alex Orailoglu:
Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains. 141-154 - Vikram B. Suresh, Sandip Kundu:
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array. 155-165 - Lechang Liu, Ramesh K. Pokharel
Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation. 166-170
Volume 35, Number 2, February 2016
- Yiqun Wang, Yongpan Liu, Cong Wang, Zewei Li, Xiao Sheng, Hyung Gyu Lee, Naehyuck Chang, Huazhong Yang:
Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things. 173-186 - Mohammad Javad Sharifi, Davoud Bahrepour:
A Multiloop and Full Amplitude Hysteresis Model for Molecular Electronics. 187-196 - André Lange
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters. 197-210 - Anwar Jarndal
A Reliable Model Parameter Extraction Method Applied to AlGaN/GaN HEMTs. 211-219 - Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. 220-231 - Xuan Dong, Lihong Zhang:
Lithography-Aware Analog Layout Retargeting. 232-245 - Seong-I Lei, Wai-Kei Mak:
Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs. 246-259 - Junxiu Liu, Jim Harkin
Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead. 260-273 - Sungyoul Seo
Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression. 274-284 - Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li
Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. 285-297 - Joon-Sung Yang, Jinsuk Chung, Nur A. Touba:
Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation. 298-308 - Mukesh Agrawal, Krishnendu Chakrabarty
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs. 309-322 - Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees. 323-336 - Irith Pomeranz:
Balancing the Numbers of Detected Faults for Improved Test Set Quality. 337-341
Volume 35, Number 3, March 2016
- Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey:
Editorial. 345 - Prajit Nandi, Hirak Talukdar, Dhiraj Kumar, Ashvinkumar G. Katakwar:
A Novel Approach to Design SAR-ADC: Design Partitioning Method. 346-356 - Trey Reece
Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules. 357-366 - Mojtaba Ebrahimi, Hossein Asadi
Layout-Based Modeling and Mitigation of Multiple Event Transients. 367-379 - Jianlei Yang
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. 380-393 - Benjamin Carrión Schäfer
Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration. 394-406 - Jason Cong, Peng Li
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. 407-418 - Alberto A. Del Barrio
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. 419-432 - Qi Guo, Tianshi Chen, Yunji Chen
Accelerating Architectural Simulation Via Statistical Techniques: A Survey. 433-446 - Fan Lan, Yun Pan, Kwang-Ting (Tim) Cheng
An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling. 447-457 - Yu-Chung Hsiao, Luca Daniel:
CAPLET: A Highly Parallelized Field Solver for Capacitance Extraction Using Instantiable Basis Functions. 458-470 - Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures. 471-484 - Xueyang Wang, Ramesh Karri
Reusing Hardware Performance Counters to Detect and Identify Kernel Control-Flow Modifying Rootkits. 485-498 - Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin:
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. 499-512 - Caio Araujo T. Campos, Abner Luis Panho Marciano, Omar P. Vilela Neto
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA. 513-517
Volume 35, Number 4, April 2016
- Tony F. Wu, Karthik Ganesan
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits. 521-534 - Firew Siyoum, Marc Geilen
End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources. 535-548 - Soumitra Pal
Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications. 549-558 - Kai Hu, Tsung-Yi Ho
Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips. 559-572 - Bajaj Ronak, Suhaib A. Fahmy:
Mapping for Maximum Performance on FPGA DSP Blocks. 573-585 - Hsuan-Ming Huang, Charles H.-P. Wen
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - From Device to Circuit Level. 586-597 - Hui-Ju Katherine Chiang, Chi-Yuan Liu, Jie-Hong R. Jiang, Yao-Wen Chang
Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification. 598-610 - Qing Xie, Donghwa Shin, Naehyuck Chang, Massoud Pedram:
Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources. 611-622 - Francesco Beneventi, Andrea Bartolini
Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip. 623-636 - Florian Sagstetter, Peter Waszecki, Sebastian Steinhorst
Multischedule Synthesis for Variant Management in Automotive Time-Triggered Systems. 637-650 - Fazal Hameed
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. 651-664 - Fangming Ye, Farshad Firouzi, Yang Yang, Krishnendu Chakrabarty
On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines. 665-678 - Zheng Gong, Rashid Rashidzadeh:
TSV Extracted Equivalent Circuit Model and an On-Chip Test Solution. 679-690 - Min Huang, Zhaoqing Liu, Liyan Qiao, Yi Wang
An Endurance-Aware Metadata Allocation Strategy for MLC NAND Flash Memory Storage Systems. 691-694
Volume 35, Number 5, May 2016
- Shiyan Hu, Xiaobo Sharon Hu
Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design. 697-698 - Bowen Zheng, Peng Deng, Anguluri Rajasekhar, Qi Zhu
Cross-Layer Codesign for Secure Cyber-Physical Systems. 699-711 - Mianxiong Dong
LSCD: A Low-Storage Clone Detection Protocol for Cyber-Physical Systems. 712-723 - Daming Zhang, Yongpan Liu, Jinyang Li, Chun Jason Xue, Xueqing Li, Yu Wang, Huazhong Yang:
Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes. 724-737 - Domenico Balsamo, Anup Das
Graceful Performance Modulation for Power-Neutral Transient Computing Systems. 738-749 - Hyung-Chan An, Hoeseok Yang, Soonhoi Ha:
A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness. 750-763 - Mirela Alistar
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures. 764-777 - Muhammad Umer Khan
CPS Oriented Control Design for Networked Surveillance Robots With Multiple Physical Constraints. 778-791 - Bin Zhou, Wei Zhang
Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique. 792-805 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Majority-Inverter Graph: A New Paradigm for Logic Optimization. 806-819 - Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. 820-831 - Qinggao Mei, Wim Schoenmaker, Shih-Hung Weng, Hao Zhuang, Chung-Kuan Cheng, Quan Chen:
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits. 832-843 - Anastasios Psarras
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels. 844-857 - Seyed Nematollah Adel Ahmadyan
Automated Transient Input Stimuli Generation for Analog Circuits. 858-871 - Emad Ebeid
Erratum to "Model-Driven Design of Network Aspects of Distributed Embedded Systems". 872
Volume 35, Number 6, June 2016
- Rishad A. Shafik, Sheng Yang, Anup Das
Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems. 877-890 - Linbo Long, Duo Liu, Liang Liang, Xiao Zhu, Kan Zhong, Zili Shao
Morphable Resistive Memory Optimization for Mobile Virtualization. 891-904 - Xue-Yang Zhu
Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding. 905-918 - Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
m-Inductive Property of Sequential Circuits. 919-930 - Stephan Weber, Tiago Ressurreicao, Cândido Duarte
Yield Prediction With a New Generalized Process Capability Index Applicable to Non-Normal Data. 931-942 - Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar
Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping. 943-956 - Srinivas Jallepalli, Ram Mooraka, Sanjay Parihar
Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling. 957-970 - Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou, Xin Li:
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree. 971-984 - Shi Jin, Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty
Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes. 985-998 - Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li
Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving. 999-1011 - Xiaobing Shi, Nicola Nicolici:
On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation. 1012-1025 - Alberto Griggio
Comparing Different Variants of the ic3 Algorithm for Hardware Model Checking. 1026-1039 - Leibin Ni, Sai Manoj P. D.
A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations. 1040-1051
Volume 35, Number 7, July 2016
- Sven Tenzing Choden Konigsmark, Deming Chen, Martin D. F. Wong
PolyPUF: Physically Secure Self-Divergence. 1053-1066 - Abhishek Basak, Swarup Bhunia
P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs. 1067-1078 - Keonsoo Ha, Jaeyong Jeong, Jihong Kim:
An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory. 1079-1091 - Hyeon Uk Sim, Hongsik Lee, Seongseok Seo, Jongeun Lee:
Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures. 1092-1104 - Kuo-Hsuan Meng, Vrashank Shukla, Elyse Rosenbaum:
Full-Component Modeling and Simulation of Charged Device Model ESD. 1105-1113 - Wangkun Jia, Brian T. Helenbrook
Fast Thermal Simulation of FinFET Circuits Based on a Multiblock Reduced-Order Model. 1114-1124 - Lucian Vintan, Radu Chis, Muhammad Ali Ismail, Cristian Cotofana:
Improving Computing Systems Automatic Multiobjective Optimization Through Meta-Optimization. 1125-1129 - Hung-I Lee, Chen-Yo Han, James Chien-Mo Li:
A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse. 1130-1137 - Li Yu, Sharad Saxena, Christopher Hess, Ibrahim Abe M. Elfadel
Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection. 1138-1150 - Di Zhu, Siyu Yue, Naehyuck Chang, Massoud Pedram:
Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use. 1151-1164 - Yun Liang, Muhammad Teguh Satria, Kyle Rupnow
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization. 1165-1178 - Kai Hu, Bhargab B. Bhattacharya, Krishnendu Chakrabarty
Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips. 1179-1191 - Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. 1192-1205 - Tim Pruss, Priyank Kalla, Florian Enescu:
Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields. 1206-1218 - Taewoo Han, Inhyuk Choi, Hyunggoy Oh, Sungho Kang:
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores. 1219-1223 - Angelo Ciccazzo, Gianni Di Pillo, Vittorio Latorre
A SVM Surrogate Model-Based Method for Parametric Yield Optimization. 1224-1228
Volume 35, Number 8, August 2016
- Mark Po-Hung Lin
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths. 1229-1242 - Hung-Chih Ou, Kai-Han Tseng, Jhao-Yan Liu, I-Peng Wu, Yao-Wen Chang
Layout-Dependent Effects-Aware Analytical Analog Placement. 1243-1254 - Fa Wang, Paolo Cachecho, Wangyang Zhang, Shupeng Sun, Xin Li, Rouwaida Kanj, Chenjie Gu:
Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data. 1255-1268 - Junlong Zhou, Tongquan Wei
Thermal-Aware Task Scheduling for Energy Minimization in Heterogeneous Real-Time MPSoC Systems. 1269-1282 - Hailong Yao, Qin Wang, Yiren Shen, Tsung-Yi Ho
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. 1283-1296 - Rui Jia, Hai-Gang Yang, Colin Yu Lin, Rui Chen
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability. 1297-1308 - Marko Magerl
Echo State Networks for Black-Box Modeling of Integrated Circuits. 1309-1317 - Ermao Cai, Da-Cheng Juan, Siddharth Garg, Jinpyo Park, Diana Marculescu
Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling. 1318-1331 - Jin-Tai Yan
Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs. 1332-1344 - Yu-Hsuan Su, Yu-Chen Huang, Liang-Chun Tsai, Yao-Wen Chang
Fast Lithographic Mask Optimization Considering Process Variation. 1345-1357 - Anup Das
Workload Change Point Detection for Runtime Thermal Management of Embedded Systems. 1358-1371 - Yubiao Pan, Yongkun Li, Yinlong Xu, Biaobiao Shen:
DCS: Diagonal Coding Scheme for Enhancing the Endurance of SSD-Based RAID Arrays. 1372-1385 - Álvaro Gómez-Pau
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space. 1386-1395
Volume 35, Number 9, September 2016
- Florin Burcea, Husni M. Habal, Helmut E. Graeb:
A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity. 1397-1410 - Muhammad Yasin
On Improving the Security of Logic Locking. 1411-1424 - Ming-Chang Yang, Yuan-Hao Chang
Graceful Space Degradation: An Uneven Space Management for Flash Storage Devices. 1425-1434 - Xiaoming Chen, Lin Wang, Boxun Li, Yu Wang, Xin Li, Yongpan Liu, Huazhong Yang:
Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation. 1435-1448 - Wei-Che Wang, Puneet Gupta
Efficient Layout Generation and Design Evaluation of Vertical Channel Devices. 1449-1460 - Ping Chi, Wang-Chien Lee, Yuan Xie:
Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory. 1461-1474 - Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu
Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. 1475-1488 - Pietro Buccella, Camillo Stefanucci, Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Michel Sallese, Maher Kayal:
Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs. 1489-1502 - Hadi Ahmadi Balef, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution. 1503-1508 - Javad Yavand Hasani
Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects. 1509-1518 - Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang:
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. 1519-1531 - Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng:
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography. 1532-1545 - Abdulazim Amouri, Jochen Hepp, Mehdi Baradaran Tahoori:
Built-In Self-Heating Thermal Testing of FPGAs. 1546-1556 - Valeriy Balabanov, Shuo-Ren Lin, Jie-Hong R. Jiang:
Flexibility and Optimization of QBF Skolem-Herbrand Certificates. 1557-1568 - Gang Wu, Chris Chu:
Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells. 1569-1573
Volume 35, Number 10, October 2016
- Kan Zhong, Duo Liu, Liang Liang, Xiao Zhu, Linbo Long, Yi Wang
Energy-Efficient In-Memory Paging for Smartphones. 1577-1590 - Razvan Nane
A Survey and Evaluation of FPGA High-Level Synthesis Tools. 1591-1604 - Jiatao Ding, Jiajia Chen, Chip-Hong Chang
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction. 1605-1617 - Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan:
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions. 1618-1629 - Ayman Yehia Hamouda, Mohab Anis, Karim S. Karim:
Model-Based Initial Bias (MIB): Toward a Single-Iteration Optical Proximity Correction. 1630-1639 - Majid Ahadi, Sourajeet Roy
Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits. 1640-1652 - Konstantis Daloukas, Nestor E. Evmorfopoulos, Panagiota E. Tsompanopoulou, George I. Stamoulis:
Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs). 1653-1666 - Gadi Oxman, Shlomo Weiss:
An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation. 1667-1680 - Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng:
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks. 1681-1694 - Denis Oyaro, Piero Triverio
TurboMOR-RC: An Efficient Model Order Reduction Technique for RC Networks With Many Ports. 1695-1706 - Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs. 1707-1720 - Yuhan Zhou, Yong Zhang, Vivek Sarin, Wangqi Qiu, Weiping Shi:
Macro Model of Advanced Devices for Parasitic Extraction. 1721-1729 - Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang:
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. 1730-1743 - Tao Wang, Chun Zhang, Jinjun Xiong
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors. 1744-1754 - Irith Pomeranz:
Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity. 1755-1762 - Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang
A New 3-D Fuse Architecture to Improve Yield of 3-D Memories. 1763-1767
Volume 35, Number 11, November 2016
- Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Partha Pratim Pande, Vincenzo Catania:
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling. 1769-1782 - Kostas Siozios
A Customizable Framework for Application Implementation onto 3-D FPGAs. 1783-1796 - Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang:
Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. 1797-1810 - Hai-Bao Chen, Sheldon X.-D. Tan, Xin Huang, Taeyoung Kim
Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees. 1811-1824 - Ahmet Gokcen Mahmutoglu, Alper Demir
Non-Monte Carlo Analysis of Low-Frequency Noise: Exposition of Intricate Nonstationary Behavior and Comparison With Legacy Models. 1825-1835 - Ya Wang
Robust and Efficient Transistor-Level Envelope-Following Analysis of PWM/PFM/PSM DC-DC Converters. 1836-1847 - Xin Huang, Armen Kteyan, Sheldon X.-D. Tan, Valeriy Sukharev
Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks. 1848-1861 - Tsung-Wei Huang, Martin D. F. Wong
UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR. 1862-1875 - Martin Lukasiewycz, Matthias Kauer, Sebastian Steinhorst
Synthesis of Active Cell Balancing Architectures for Battery Packs. 1876-1889 - Xue Lin, Yanzhi Wang, Naehyuck Chang, Massoud Pedram:
Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting. 1890-1902 - Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis:
ATPG for Delay Defects in Current Mode Threshold Logic Circuits. 1903-1913 - Zahi Moudallal, Farid N. Najm:
Generating Current Budgets to Guarantee Power Grid Safety. 1914-1927 - Antara Ain, Antonio Anastasio Bruto da Costa, Pallab Dasgupta:
Feature Indented Assertions for Analog and Mixed-Signal Validation. 1928-1941 - Debao Wei, Libao Deng, Peng Zhang, Liyan Qiao, Xiyuan Peng:
NRC: A Nibble Remapping Coding Strategy for NAND Flash Reliability Extension. 1942-1946
Volume 35, Number 12, 2016
- Haeseung Lee, Mohammad Abdullah Al Faruque
Run-Time Scheduling Framework for Event-Driven Applications on a GPU-Based Embedded System. 1956-1967 - Domenico Balsamo
Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices. 1968-1980 - Tsun-Ming Tseng
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips. 1981-1994 - Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation. 1995-2007 - Shouzhen Gu, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Yiran Chen, Jingtong Hu
A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems. 2008-2017 - Vincenzo Rana
Efficient Hardware Design of Iterative Stencil Loops. 2018-2031 - Ying Chen, Tan Nguyen, Yao Chen
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. 2032-2045 - Jea Woo Park
Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space. 2046-2055 - Taigon Song
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs. 2056-2067 - Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim:
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. 2068-2081 - Qiushi Han
Temperature-Constrained Feasibility Analysis for Multicore Scheduling. 2082-2092 - Baris Arslan, Alex Orailoglu:
Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment. 2093-2103 - Stephan Eggersglüß
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. 2104-2117 - Pouya Taatizadeh, Nicola Nicolici:
Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation. 2118-2130 - Cunxi Yu
Formal Verification of Arithmetic Circuits by Function Extraction. 2131-2142 - Ke Huang, Jian Wen, Jim Willmore:
Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation. 2143-2147 - Changhai Liao, Jun Tao, Handi Yu, Zhangwen Tang, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li:
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. 2148-2152
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