Simple high-level synthesis of portable Verilog directly from idiomatic imperative Python for numerical/DSP-heavy applications. Not an HDL.

Tiny Tapeout ASIC: Double balanced mixer for 7 MHz and a quadrature divider using Sky130 technology.

🛜 ESPectre 👻 - Motion detection system based on Wi-Fi spectre analysis (CSI), with Home Assistant integration.

A collection of my XR prototypes as apk files for Meta Quest devices.

A GPU with transformation & lighting, rasterization, texture mapping, flat shading, double buffer, z-buffer

Parsing gigabytes of JSON per second : used by Facebook/Meta Velox, the Node.js runtime, ClickHouse, WatermelonDB, Apache Doris, Milvus, StarRocks

New clean hdmi implementation for ulx3s, icestick, icoboard, arty7, colorlight i5 and blackicemx! With tmds encoding hacked down from dvi standard. Supports DDR and SRD tranfser!

ngscopeclient and other client applications for libscopehal.

Towards an Automated Triple Modular Redundancy (TMR) EDA flow for Yosys.

An open source GPU based off of the AMD Southern Islands ISA.

A Risc-V SoC for Tiny Tapeout

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

An ECP5 FPGA Dev Board in a Pi Zero form

Build your hardware, easily!

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

The complete codebase for Frame

RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34

Open Logic FPGA Standard Library

Vitis HLS LLVM source code and examples

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

A minimal GPU design in Verilog to learn how GPUs work from the ground up

👾 Complete Quartus Project for FPGA-based-3D-renderer

Machine learning on FPGAs using HLS

Вектор-06ц в ПЛИС / Vector-06c in FPGA