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Showing results

Multiplayer CMOS Standard Cell Chips Reverse Engineering Tool

TypeScript 122 6 Updated Jun 12, 2026

MOS 6581 / 8580 SID software emulator

C 77 6 Updated May 20, 2023

A library to play Commodore 64 music

C++ 101 24 Updated Jul 17, 2026

Modern IRC Client for the web, desktop and mobile.

TypeScript 223 21 Updated Jul 20, 2026

Bound Book Format: A high-performance container format for comics and manga

C 405 5 Updated Feb 7, 2026
Verilog 9 Updated Jan 18, 2026

Run your GitHub Actions locally 🚀

Go 71,207 1,984 Updated Jul 10, 2026

☕ GDBFrontend is an easy, flexible and extensible gui debugger.

JavaScript 3,025 112 Updated Nov 12, 2025

FM synth reverse-engineering

91 3 Updated Oct 1, 2023

Highly accurate Yamaha OPL3 (YMF262, CT1747) emulator

C 239 29 Updated Jul 1, 2024

Simulation model of the Atari STE GSTMCU

Verilog 12 2 Updated Jan 2, 2025

Optical character recognition for Japanese text, with the main focus being Japanese manga

Python 2,726 135 Updated Jul 19, 2026

GammaRay is a tool to poke around in a Qt-application and also to manipulate the application to some extent.

C++ 1,903 327 Updated Jul 20, 2026

ATARI-ST SNDH Archive music browser/player

C++ 57 6 Updated Jul 12, 2026

Activate any version of Windows and Office, forever

Dockerfile 2,250 194 Updated Oct 23, 2025

KiCad Libraries for Würth Elektronik Products

107 9 Updated Jul 14, 2026

draws an SVG schematic from a JSON netlist

JavaScript 809 107 Updated Jan 25, 2024

Stacker is a static analysis tool for analyzing the amount of stack space used by a program.

Python 12 2 Updated Jun 5, 2023

🚀 Level up your GitHub profile readme with customizable cards including LOC statistics!

Python 15,998 116 Updated Jan 25, 2025

Static analyzer for C/C++ based on the theory of Abstract Interpretation.

C++ 3,158 218 Updated May 31, 2026

WAL enables programmable waveform analysis.

Python 182 26 Updated May 31, 2026

An open-source remote desktop application designed for self-hosting, as an alternative to TeamViewer.

Rust 118,850 18,122 Updated Jul 25, 2026

Smol 2-stage RISC-V processor in nMigen

Python 26 2 Updated May 6, 2021

Minimal RV32I processor with register file in RAM

Verilog 4 1 Updated Sep 10, 2022

Example Hazard3 + OpenDAP RISC-V SWD SoC integration

Verilog 11 1 Updated Apr 20, 2023

5-stage RISC-V CPU, originally developed for RISCBoy

Verilog 39 1 Updated Jul 1, 2023

Carrier for Blackpill F411 when used as Blackmagic Probe

4 1 Updated Oct 3, 2024

3-stage RV32IMACZb* processor with debug

Verilog 1,078 89 Updated Jul 21, 2026

A flexible (literally) interface for connecting FPGA modules.

6 Updated May 27, 2024
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