Convert sigrok recording to sal for analysis in logic2

based on getmail 5.14, with adaptations for python 3

A tool for integrating Git with Patchwork, the web-based patch tracking system

A patch email tracking and testing system

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

Elegantly record your screen

Experimental USB2 HS/FS host primitives for FPGAs.

The https://fpgas.online website

Entry point for issues and wiki. Also contains some scripts and sources.

A high-performance RISC-V dual-core MCU (Qingke V5F + V3F) with 400MHz frequency/896KB SRAM/960KB Flash/CoreMark 5.73/MHz

Allow some tests to be described as unstable. That means pytest will return 0 even if those tests failed.

Blob-free logic analyzer firmware for FX3

LatticeMico32 and Milkymist port for NetBSD

Launch apps by casting spells! 🪄

CologneChip GateMate FPGA Module: GMM-7550

Python interface to OpenEMS, for PCB trace simulation. Accepts Gerber files as input. Features automatic grid generation and postprocessing.

draws an SVG schematic from a JSON netlist

❄️ Visual editor for open FPGA boards

Read-only mirror of the official repo at git://sigrok.org/pulseview. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

iCESugar FPGA Board (base on iCE40UP5k)

Source code of apps.yunohost.org

Read-only mirror of the official repo at git://sigrok.org/libsigrok. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

Open source Logic Analyzer based on LiteX SoC

WCH CH56x BSP for HydraUSB3 v1 hardware

A Linux-capable RISC-V multicore for and by the world

Small utility to dump RISC-V supported extensions using __riscv_hwprobe() syscall

A tiny Open POWER ISA softcore written in VHDL 2008