Stars
A simple timetracker for the command line. It saves a log of all tracked activities as a plaintext file and allows you to create flexible reports.
Entrada RL 2024
A graphical processor simulator and assembly editor for the RISC-V ISA
Random instruction generator for RISC-V processor verification
Chisel: A Modern Hardware Design Language
RISC-V Formal Verification Framework
Functional verification project for the CORE-V family of RISC-V cores.
RARS -- RISC-V Assembler and Runtime Simulator
Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our…
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
Must-have verilog systemverilog modules
A repository of gate-level simulators and tools for the original Game Boy.
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Verilog to Routing -- Open Source CAD Flow for FPGA Research
[MIRROR] Sample-Server implementation based on open62541, showcases umati endorsed OPC UA companion specifications. Provides a 🐋 📦 to run locally for development purpose.
Esse repositório foi criado para organizar todos os repositórios de eventos do Turing USP.
🖼️ A command-line system information tool written in bash 3.2+
Verilator open-source SystemVerilog simulator and lint system
Project F brings FPGAs to life with exciting open-source designs you can build on.
a small build system with a focus on speed