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1. RV32I-Pipline-CPU-trace-JYD RV32I-Pipline-CPU-trace-JYD Public

   第九届全国大学生集成电路创新创业大赛——数字SoC设计赛道竞业达杯作品（华南赛区二等奖）

   SystemVerilog 30 2

2. PYNQ-OpenSource-Template PYNQ-OpenSource-Template Public

   Forked from vickyiii/PYNQ-OpenSource-Template

   全国大学生嵌入式芯片与系统设计竞赛-FPGA创新设计大赛AMD命题式基础赛道决赛作品（全国一等奖）

   8

3. BigBird-CPU-Lab BigBird-CPU-Lab Public

   BigBird: A Beginner-Friendly RV32I CPU Tutorial.The really zero-to-cpu

   SystemVerilog 13 1

4. Prompt-Set-Design Prompt-Set-Design Public

   (ISEDA 2026 Singapore) A three-stage Prompt template library for FPGA/Vitis HLS: from algorithm translation and structure optimization to board-level integration, it helps readers quickly adapt and…

   C++ 1

5. hlstrack2025_40562 hlstrack2025_40562 Public

   全国大学生嵌入式芯片与系统设计竞赛-FPGA 创新设计大赛AMD命题式基础赛道初赛决赛作品合集（全国一等奖）

   C++ 5

6. riscv-dsp-processor riscv-dsp-processor Public

   Forked from abhikm35/riscv-dsp-processor

   Custom RISC-V DSP Processor with MAC, SIMD, and FFT capabilities

   Verilog