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VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

TypeScript 37 Updated Nov 6, 2025

Show where time is wasted during the context upload of `docker build`

Go 345 17 Updated Apr 12, 2021

A low-level virtualization interface for Linux-based systems using WebAssembly

C 190 20 Updated May 15, 2026

Terraform module for scalable GitHub action runners on AWS

TypeScript 3,053 727 Updated May 15, 2026

Enable locally-located assets in Nuxt Content

TypeScript 123 14 Updated Feb 11, 2026

HIBA is a system built on top of regular OpenSSH certificate-based authentication that allows to manage flexible authorization of principals on pools of target hosts without the need to push custom…

C 388 18 Updated May 28, 2025

A language that compiles to Bash and Windows Batch

OCaml 4,350 167 Updated Apr 30, 2023

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,876 736 Updated May 7, 2026

OpenTitan: Open source silicon root of trust

SystemVerilog 3,366 1,006 Updated May 17, 2026

Scan, index, and archive all of your paper documents

Python 7,919 502 Updated Apr 6, 2021

OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores

C 88 26 Updated Mar 8, 2021