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Like VexRiscv, but, Harder, Better, Faster, Stronger
A FPGA friendly 32 bit RISC-V CPU implementation
An open source, self-hosted implementation of the Tailscale control server
FROST (FPGA RISC-V Open-sourced in SystemVerilog by TwoSigma)
Website for Systems Research Seminar at UIUC
This repo is a mirror of the official userspace-rcu git found at git://git.lttng.org/userspace-rcu.git. liburcu is a LGPLv2.1 userspace RCU (read-copy-update) library. This data synchronization lib…
The FreeBSD src tree publish-only repository. Experimenting with 'simple' pull requests....
A bare minimum hypervisor on AMD and Intel processors for learners.
Asterinas aims to be a production-grade Linux alternative—memory safe, high-performance, and more.
Rex is a safe and usable kernel extension framework that allows loading and executing Rust kernel extension programs in the place of eBPF.
Rusty Hypervisor - Windows UEFI Blue Pill Type-1 Hypervisor in Rust (Codename: Illusion)
A versatile, performance-oriented generic hash table library for C.
Push-Button End-to-End Testing of Kubernetes Operators and Controllers
C++14 concurrent lock-free low-latency queue.
Lightweight web-based CPUID decoder and visualiser.
A modern and intuitive terminal-based text editor
Carbon Language's main repository: documents, design, implementation, and related tools. (NOTE: Carbon Language is experimental; see README)
Home of the simple console library consisting of ProgressBar, Window, Form, Draw & MockConsole (C# console progress bar with support for single or multithreaded progress updates) Window is a 100%-i…