Design of High-Performance Q1.7 Fixed-Point Quantized CNN Hardware Accelerator with Microarchitecture Optimization of 3-Stage Pipelined Systolic MAC Arrays for Lightweight Inference

A fully synthesizable INT8 CNN accelerator for CIFAR-10, built around a 3-stage pipelined systolic-array MAC microarchitecture optimized from a 6-design PPA benchmark. Includes complete quantization workflow (PTQ/QAT), 2-cycle ready/valid protocol, ROM automation, FP32↔RTL accuracy checks, and a hardware image-processing suite

" I tried to ImProVe, but NeVer really did - so I MOVe-d on ¯\_(ツ)_/¯ "

Current Project Overview

Duration: Individual, Ongoing
Tools: Verilog (Icarus Verilog, Yosys) | Python (TensorFlow, NumPy) | Scripting (TCL, Perl)

8-bit Quantized CNN Hardware Accelerator: Open-source, Modular, & Optimized for Inference

Project Link Verilog | Basic Architecture | Digital Electronics

• Designed a fully synthesizable shallow Res-CNN for CIFAR-10, evaluated against eight reference CNNs, and achieved a Pareto-optimal trade-off across throughput, latency, and accuracy.

• Implemented systolic-array processing elements using 8-bit CSA–MBE MAC units with FSM-driven control logic and a 2-cycle read/valid handshake. Verified end-to-end datapath behavior through structured testbenches.

• Performed detailed post-training quantization (PTQ) and quantization-aware training (QAT) studies. Quantizing from Q1.31 to Q1.3 allowed exploration of precision vs. accuracy trends, and a Q1.7 PTQ model retained ~84% accuracy (less than 1% drop) while reducing the model memory footprint by 4× (≈52 kB).

• Developed automated scripts (TCL + Python) to generate 14 coefficient ROMs and 3 RGB input ROMs, enabling seamless hardware ingestion of model parameters and images. Verified TensorFlow / FP32 ↔ RTL output consistency and automated full-pipeline inference execution.

• Built a compact digital image-processing toolkit (edge detection, denoising, filtering, enhancement) and an MLP classifier for (E)MNIST datasets. Achieved >75% accuracy with real-time GUI visualization for interactive experimentation.

High-Speed 3-Stage Pipelined Systolic Array-Based MAC Architectures

Digital Logic Design | Synthesis

• Benchmarked six different 8-bit signed adder–multiplier architectures using PPA metrics (latency, throughput, and area) on the Sky130 PDK, and analyzed their architectural trade-offs in the context of low-power convolution workloads.

• Designed a 3-stage pipelined systolic MAC based on a CSA–MBE multiplier structure, achieving substantial improvements over a naïve conv3 baseline: 66.3% lower delay, 3.1× higher area efficiency, and 82.2% lower typical power.

• Implemented a 2D systolic PE-grid supporting general convolution and GEMM operations, with verified behavior under zero-padding and same-padding configurations. GEMM optimization reduced power consumption by 44.6% for matrix dimension (N = 3).

• Integrated a 648-bit scan chain spanning all pipeline and control registers, enabling full DFT/ATPG support with only 14.5% cell-area overhead, ensuring manufacturability and high test coverage.

Repositories

ViSiON – Verilog for Image Processing and Simulation-based Inference Of Neural Networks

This repo includes all related projects as submodules in one place

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ImProVe – IMage PROcessing using VErilog: A collection of image processing algorithms implemented in Verilog, including geometric transformations, color space conversions, and other foundational operations.

NeVer – NEural NEtwork on VERilog: A hardware-implemented MLP in Verilog for character recognition on (E)MNIST, alongside a lightweight CNN for CIFAR-10 image classification

MOVe – Math Ops in VErilog

• CORDIC Algorithm – Implements Coordinate Rotation Digital Computer (CORDIC) algorithms in Verilog for efficient hardware-based calculation of sine, cosine, tangent, square root, magnitude, and more.

• Systolic Array Matrix Multiplication – Verilog implementation of matrix multiplication using systolic arrays to enable parallel computation and hardware-level performance optimization. Each processing element leverages a Multiply-Accumulate (MAC) unit for core operations.

• Hardware Multiply-Accumulate Unit – Implements and compares 8-bit multipliers and 8-bit adders in synthesizable Verilog, analyzing their area, timing, and power characteristics in MAC datapath architectures.

• Posit Arithmetic (Python) – Currently using fixed-point arithmetic; considering Posit as an alternative to IEEE 754 for better precision and dynamic range. Still working through the trade-off.

Storage and Buffer Modules

• RAM1KB – A 1KB (1024 x 8-bit) memory module in Verilog with write-once locking for even addresses. Includes a randomized testbench. Also forms the base for a ROM3KB variant to store 32×32 RGB CIFAR-10 image data.

• FIFO Buffer – Not started. Planned as a synchronous FIFO with fixed depth, single clock domain, and standard full/empty flag logic.

RV32I RISC-V Core (TL-Verilog, Single-Cycle Implementation)

Tools: Makerchip | TL-Verilog | Verilator

• Implemented a RV32I single-stage core supporting all base integer instructions across I, S, B, U, J, and R formats.
• Designed a 32×32 register file with dual-read / single-write ports, enforcing x0 = 0 invariance.
• Implemented ALU operations covering arithmetic, logical, shift, and compare paths with correct immediate decode (opcode / funct3 / funct7).
• Verified via a test program summing integers 1–9, completing within ~50 cycles, updating pass/fail status in x30 and x31.
• Integrated interactive simulation support via m4+cpu_viz(), enabling cycle-accurate register/memory visualization.

RV32I RISC-V Core (Verilog, Single-Cycle Implementation)

Tools: Verilog | Icarus Verilog | ModelSim | Quartus Prime

• Designed a 32-bit single-cycle RV32I core with modular datapath: ALU, control, immediate generator, PC logic, instruction & data memories.
• Implemented all 38 base instructions including full load/store support: LB, LBU, LH, LHU, LW, SB, SH, SW, with correct zero/sign extension and RMW correctness.
• Verified correctness using self-checking ModelSim testbenches and synthesized the core on Quartus Prime.

MIPS Microarchitectures - SC / MC / 5-Stage Pipeline

Tools: Verilog | Icarus Verilog | ModelSim | GTKWave

• Implemented three 32-bit MIPS processors:

  • Single-Cycle: CPI = 1.0, PC increments by +4 each cycle.

  • Multi-Cycle: Instruction class cycle counts:

    • R-type: 4 cycles
    • I-type arithmetic: 4 cycles
    • Load: 5 cycles
    • Store: 4 cycles
    • Branch: 3 cycles
    • Jump: 3 cycles → Benchmark CPI ≈ 4.1

  • Pipeline (IF–ID–EX–MEM–WB): forwarding, hazard detection, 1-cycle load-use stall, 1-cycle taken-branch flush. → Benchmark CPI ≈ 1.1–1.2

• Executed Harris & Harris benchmark (18 instructions). Correctly wrote 0x00000007 to memory addresses 0x50 and 0x54.

• Included self-checking benches, .mem loading infrastructure, full waveforms, and verification logs.

Dual-Issue 16-bit RISC Superscalar Processor (In-Order)

Tools: Verilog | Icarus Verilog | GTKWave

• Implemented a two-wide in-order superscalar processor with parallel IF–ID–EX–MEM–WB lanes and independent pipeline registers per lane.
• Instruction fetch returns 32 bits = 2×16-bit instructions; dependency checks suppress lane-1 when hazards exist.
• Register file: 4 read ports + 2 write ports, with r0=0 hardwired.
• Hazard handling: RAW/WAW detection, load-use stall insertion, inter-lane dependency checks, branch squashing.
• Memory system: multi-port (three-port ARAM) enabling simultaneous instruction fetch + data access.
• Verified using program that sums 1–10 → final register value r1 = 0x0037 (55) with correct inter-lane suppression due to true dependencies.

Repositories

A synthesizable CORDIC-based trigonometric IP supporting sin, cos, and tan evaluation using a parameterized fixed-point rotation core. Includes standalone wrappers, arctan lookup ROM, and a verification environment with angle sweeps and floating-point correlation.

CORDIC Trigonometric Soft IP - Parametric Fixed-Point Core + Wrapper Functions

Duration: Individual
Tools: Verilog | Icarus Verilog | FuseSoC

• Implemented a fully synthesizable fixed-point CORDIC core (iterative rotation mode) supporting configurable datapath width, iteration count, and shift-add update logic.
• Created sin, cos, tan wrappers around the base CORDIC core, each applying pre-scaled initial vectors to cancel CORDIC gain and produce Q-format outputs (Q1.15 for sin/cos, Q3.28 for tan).
• Integrated a precomputed 16-entry atan(2⁻ᵢ) ROM table using signed 32-bit constants in Q3.29 format for angle accumulator updates.
• Designed the core using shift-add micro-rotations only (no multipliers), enabling low-resource FPGA use and ASIC DSP embedding.
• Verification testbench sweeps angles from −1.5 to +1.5 rad in 0.1 increments, comparing fixed-point outputs with double-precision math.
  • Max error: sin ≈ 3.9×10⁻⁵, cos ≈ 4.5×10⁻⁵
  • RMS error: sin ≈ 2.0×10⁻⁵, cos ≈ 2.8×10⁻⁵
  • tan diverges as expected near ±π/2 (max ≈ 6.10).
• Supports FuseSoC integration for one-command builds and simulation.

Implemented a collection of peripheral serial communication interfaces in Verilog, focusing on synthesizable, parameterizable controllers suitable for FPGA/ASIC integration. Each protocol includes a cleanly modularized interface, configurable timing parameters, and testbench-driven validation with waveform inspection.

• I2C Master Controller – Implements a single-master, multi-slave I²C bus supporting standard-mode timings, programmable SCL low/high periods, ACK/NACK handling, and clock stretching detection. Features deterministic START/STOP generation, byte-wise transfers, and address+data framing logic.

• SPI Master (Modes 0–3) – Supports CPOL/CPHA mode selection, 8-bit full-duplex transfers, configurable SCLK division, selectable slave-select behavior, and MSB-first shifting. Designed with a compact FSM and separate TX/RX shift registers for predictable cycle behavior.

• UART TX Soft-Core IP – Lightweight serial transmitter with baud-rate generator, start/stop framing, data-valid gating, and FIFO-less single-byte serialization. Fully synthesizable and intended as a drop-in peripheral for SoCs, teaching cores, or FPGA peripheral sets.

Repositories

A work-in-progress open-source Python package implementing foundational DFT/Fault-modeling utilities for ISCAS’85 and ISCAS’89 benchmark circuits.
Includes automatic Verilog netlist generation, random testbench creation, serial/parallel fault simulation, fault collapsing, SCOAP metric computation, and initial ATPG experimentation. PODEM implementation is under development.

• Generates structural Verilog (.v) files and matching randomized testbenches from ISCAS netlists; injects stuck-at faults using ID-indexed assign overrides appended to the generated modules.
• Implements serial fault simulation and parallel bit-packed fault simulation, enabling coverage estimation under random vector sets.
• Automated reporting: coverage tables, detected/undetected fault lists, fault dictionaries, and comparison across vector batches.
• Supports fault collapsing using dominance & equivalence relations; identifies FFR-based partitions and reduces fault sets prior to simulation.
• Computes SCOAP controllability (CC0/CC1) and observability (CO) metrics for every internal node, enabling analysis of circuit hard-to-control or hard-to-observe regions.
• Initial ATPG experiments performed using SCOAP-guided heuristics; current PODEM implementation is incomplete due to recursion termination issues being debugged.
• Planning to add scan-chain insertion workflows for ISCAS’89 sequential circuits, enabling full-scan ATPG comparisons with random simulation.

Repositories

A parameterizable FIR filter acceleration block designed for Microwatt/OpenFrame systems. Implements a sequential multiply accumulate datapath, programmable coefficients, and a clean Wishbone-Lite register interface for CPU control. The design was accepted for potential fabrication during the hackathon review. The final taped-out submission was not completed due to timing constraints.

FIR Accelerator - Sequential Fixed-Point Filtering Unit

Duration: Hackathon submission Tools: Verilog | Icarus Verilog | Microwatt/OpenFrame

• Implements an N-tap FIR filter using time-multiplexed fixed-point multiply accumulate updates.
• Uses a shift register sample buffer and a coefficient register file loaded by Wishbone writes.
• Performs one multiply-add per cycle until all taps have been accumulated.
• Produces a fixed-width output using deterministic saturation or truncation.
• CPU interacts entirely through a compact CTRL / STATUS / DATAOUT register set.
• Optional FIFO allows input samples to be queued for continuous operation.
• Designed to be synthesizable for FPGA and Sky130 ASIC flows.

A collection of beginner-friendly ASIC design experiments where I am still learning the full RTL to GDS flow. I automated synthesis steps, generated schematic views, pushed complete flows through OpenLane and OpenROAD, produced layout snapshots, and verified the final GDS outputs. Both designs behave as compact test vehicles for understanding physical design stages and polishing my flow setup.

ASIC RTL2GDS Practice Projects

Duration: Individual Tools: Yosys | OpenLane | OpenROAD | Magic | KLayout

• Built small RTL blocks and pushed them through end-to-end ASIC flows using Sky130 PDK.
• Automated synthesis scripts to consistently generate mapped netlists, hierarchy views, and clean schematic diagrams.
• Drove OpenLane through floorplanning, placement, routing, and signoff runs, adjusting config files and verifying logs as I progressed.
• Produced DEF and GDS files, inspected them in KLayout and Magic, and validated the generated layouts.
• Exported final visuals, converted SVGs to PNGs, and organized the repository for easy inspection.
• Used both projects as training grounds to understand timing reports, flow stages, and PDN setup.
• Overall goal is learning, improving, and building confidence with complete ASIC implementation flows.

Repository Cards

A focused functional verification environment built around the open-source SHA256 core from secworks. I created a structured suite of directed, random, corner-case, and negative fail-case tests, automated through a TCL-driven flow that compiles, runs, checks, and aggregates results. The goal was to push the core through a wide coverage surface, verify digest correctness, exercise interface timing, and validate the robustness of the verification infrastructure itself.

Verification Summary

Duration: Individual Tools: Verilog | Icarus Verilog | TCL automation

• Implemented a unified verification environment with fully self-checking testbenches.
• Automated all compilation and simulation using TCL so that every test runs in a single command.
• Verified correct digest generation for standard, multi-block, random, and corner-case stimuli.
• Stressed control behavior by injecting malformed sequences, undefined values, and reversed block ordering.
• Collected per-test logs and a consolidated summary to rapidly detect regressions.
• Treated testbench infrastructure as a verification target by validating mismatch detection and protocol violation handling.

Verification Coverage

• Single-block digest generation for standard vectors
• Multi-block message chaining and state propagation
• Randomized 512-bit stimuli to probe broad input space behavior
• Corner patterns including all-zero, all-one, and alternating data
• Mode selection behavior across supported operational modes
• Protocol timing correctness for control signals
• Intentional failure injection to test mismatch handling and robustness

Automation Workflow

The TCL flow executes the entire suite:

compile all tbs
run all tests
collect logs
summarize results

This produces structured outputs with test names, expected vs actual digests, and overall regression status.

Performed semiconductor device modeling using Synopsys Sentaurus for foundational structures including N-type resistors, PN diodes, and NMOS transistors. Explored how doping profiles, junction depths, geometry parameters, and physical models impact device characteristics through calibrated simulations and scripted workflows.

• Built parameterized device structures (concentration profiles, implant energies, lateral/vertical dimensions) using Sentaurus Structure Editor and process definition files.
• Configured Sentaurus Device with transport and recombination models (SRH, Auger, mobility models, incomplete ionization where relevant) to study semiconductor behavior under applied bias.
• Automated simulation runs in Sentaurus Workbench using command-based .cmd and .des scripts for sweeping doping levels, voltages, and geometry parameters.
• Analyzed simulation output with Sentaurus Visual/Inspect, examining electrostatic potential maps, electron/hole concentration distributions, electric field intensity, and I–V characteristics.
• Extracted device metrics such as diode forward/reverse characteristics, NMOS transfer/output curves, threshold behavior, and resistance scaling for the N-type resistor.

A complete CMOS inverter implementation built using Magic VLSI (SCMOS) for physical layout and ngspice for extracted-device simulation.
Covers device construction rules under the SCMOS process, physical layout of PMOS/NMOS devices, contact/tap structures, parasitic-aware extraction, and transient analysis of inverter switching characteristics.

The layout follows the SCMOS ruleset:

• PMOS implemented inside an n-well using p-diffusion; body tied to the well tap (VDD).
• NMOS implemented directly in the p-substrate using n-diffusion; body tied to substrate tap (GND).
• Poly crossing active regions forms the MOS channel; poly, metal1, and contact stack-up follows SCMOS vertical connectivity.
• Metal1 routes input/output rails; taps ensure reverse-biased junctions and latch-up prevention.

Extraction produces a transistor-level .spice netlist including geometry-derived parasitics.
Transient simulation evaluates:

• Static noise margins and switching point displacement due to device sizing.
• Rise/fall asymmetry from mobility difference (μₙ ≫ μₚ).
• Output slew vs. load capacitance and PMOS/NMOS drive ratio.
• Propagation delays under 1.8 V operation using level-1 MOS models.

The repository includes the Magic layout (.mag), extracted netlists, wrapper files for stimulus, and generated ngspice waveforms.

Repository

A two-stage CMOS op-amp designed in TSMC 180 nm, using an NMOS differential input pair with PMOS current-mirror load, followed by a common-source second stage. Frequency compensation is implemented using a Miller capacitor between the first-stage output and the second-stage output node, producing dominant-pole behavior and stable unity-gain operation.

Device dimensions were set from closed-form analog constraints:

• Slew-rate requirement → tail bias current and overdrive allocation
• GBW requirement → input-pair transconductance and C_C relationship
• ICMR bounds → saturation margins for the differential pair and tail device
• Output swing → overdrive and saturation limits for the second stage
• Pole-splitting → ratio gₘ₆/C_C and non-dominant pole placement

Simulation results:

• Open-loop gain: ~53.1 dB
• Unity-gain bandwidth: ~4.35 MHz
• Dominant pole: ~9.6 kHz
• Phase margin: ~60° with Miller compensation
• Slew rate: ~10 V/µs from I_bias/C_C
• Output swing: ~0.14 V to ~1.03 V (linear region, no distortion at 1 kHz)
• CMRR: ~32 dB
• PSRR: +64.6 dB / –80.8 dB
• Power consumption: ~1 mW with ±2.5 V rails

Operating-point analysis confirms all MOS devices remain in saturation with expected overdrive values, and both transient and AC characteristics match analytical pole/zero predictions for a Miller-compensated two-stage topology.

A 5-stage CMOS inverter ring used as a voltage-controlled delay line, producing oscillation whose frequency scales with the control voltage. A 3-stage buffer isolates the oscillator core and restores the internal sine-like waveform into a full-swing CMOS square wave.

The oscillator operates from 0.7–3.0 V control input and shows a monotonic delay reduction with increasing drive strength.

Measured characteristics

• Frequency range: 0.724–1.93 GHz
• Linear KVCO region: ~2.1 GHz/V for 0.7–1.2 V
• Frequency saturation: begins above ~1.8 V as inverter delay approaches its minimum
• Core waveform: ~0.3–1.7 V swing with rounded edges
• Buffered output: 0–1.8 V square wave, ~50% duty cycle
• Startup time: ~0.5–0.8 ns to reach steady oscillation
• Simulation sweep: confirmed monotonic f–V relation and early compression through parametric input stepping

Frequency points

A multi-waveform analog function generator built using discrete op-amp blocks (TL082), passive RC networks, and a CD4051 analog multiplexer. The generator produces sine, square, and triangular outputs and exposes continuous control of amplitude, DC offset, and phase. Additional AM/PM blocks and a relaxation-oscillator VCO extend the system for modulation experiments.

The signal path is fully modular-each block is buffered to avoid inter-stage loading errors, enabling predictable behavior across a 1 kHz–500 kHz operating band.

Measured characteristics

• Waveforms: sine, square (<200 ns rise/fall), triangle
• Frequency range: ~1 kHz → 500 kHz (Wien-bridge tuned)
• Amplitude control: ±10 V
• DC offset range: ±5 V
• Phase control: 0°–160° (first-order all-pass)
• Square-wave performance: clean CMOS-level transitions, rise/fall < 200 ns
• Triangular output: linear ramps from integrator with controllable slope
• Waveform switching: CD4051 mux with low ON-resistance routing
• Hardware validation: TI ASLK Pro bench + LTspice simulations
• Modulation: AM/PM blocks implemented as additive/multiplicative stages
• VCO: relaxation-oscillator variant providing voltage-to-frequency behavior

Signal-generation architecture

• Wien-bridge core → low-distortion sine
• Schmitt trigger → rail-to-rail square
• Op-amp integrator → triangular
• CD4051 multiplexer → waveform selection
• Offset summer → adjustable vertical shift
• RC all-pass → continuous phase control
• Unity-gain buffers → isolate every stage and preserve amplitude accuracy

Representative measurements

• Sine output distortion minimal across most of the band; clean 1.55 kHz fundamental (LTspice + CRO)
• Square-wave rise/fall < 200 ns across load conditions
• Triangle linearity maintained through full amplitude range
• Phase shift examples captured at 64°, 90°, and ~162° using tuned RC values
• Offset correctness demonstrated for 0 V, +1 V, –1 V injected shifts

An analog PID controller built using high-linearity op-amps (LT1007 / TL082) and RC networks, implemented entirely in continuous time and validated through LTspice. The design focuses on stable low-frequency integration, controlled differentiation without noise peaking, and diode-based output limiting for robust transient behavior.

Two complete controller variants were implemented-one minimal, one extended with gain scaling and anti-windup.

Measured / designed characteristics

• Differential stage: unity-gain differential amplifier with high CMRR for clean error sensing

• Integrator: 10 ms time constant →

  • (K_i \approx 100\ \text{s}^{-1})
  • (f_c \approx 16\ \text{Hz})
  • Loop-gain boost ≈ 9.5 dB

• Derivative network: RC shaping with controlled high-frequency roll-off to prevent noise amplification

• Output swing protection: diode clamps maintaining bounded actuation signal under large transients

• Op-amp choices: LT1007 for low noise and precision; TL082 as a low-cost, wide-bandwidth alternative

• Simulation: full closed-loop Bode, transient, load-step and saturation recovery tests in LTspice

Second PID variant

• 10× front-end gain for small-signal plant feedback
• Dual-integrator configuration for deeper low-frequency suppression
• Anti-windup: diode shunts + soft-limiting network to prevent integrator runaway
• Stable recovery under saturation and high-error conditions

Design intent

• preserve linearity and phase margin across low-frequency operation
• condition derivative action to avoid overshoot due to high-frequency noise
• offer two architectures: a clean textbook PID and a high-authority PID with controlled limiting

A sub-2 kg autonomous quadrotor designed for GNSS-denied navigation, visual–inertial localization, mapping, and safe-zone landing, using onboard compute, stereo sensing, and redundant measurement sources.

Duration: Team-Based (ISRO RIG), Ongoing
Tools: Jetson Nano | Pixhawk 4 | RealSense D435i | ESP32 (ESP-Now) | ORB-SLAM3 | VINS-Fusion | ROS2

Autonomous Quadrotor for GPS-Denied Operation

• Built a <2 kg quadrotor integrating Jetson Nano for onboard processing and Pixhawk 4 for attitude/stability, targeting GNSS-denied missions requiring drift-constrained localization and controlled landing.
• Completed ESC calibration, thrust-balancing, and regulated 5 V / 3 A power distribution using BEC modules for stable sensor/compute operation under load variations.
• Integrated barometer, optical flow, and stereo-IMU sensing for multi-source position estimation with fallbacks against low-texture drift.
• Fused RealSense D435i stereo + IMU using VINS-Fusion (ROS2) and evaluated against ORB-SLAM3, achieving <5 cm drift over ~5 m trajectories in indoor GNSS-denied tests.
• Implemented ESP-Now telemetry using ESP32 modules with ~500 m LOS range for transmitting state, estimation residuals, and system health.
• Verified autonomous landing on 1.5 m × 1.5 m clear regions and tolerances up to ~15° surface inclination.
• Simulated Mars-like flight (~0.38 g gravity, no-GPS) in Webots, validating drift behavior, landing accuracy, sensing degradation, and control limits.

Repositories

ANAV – ISRO IRoC-U 2025 Autonomous Drone System

A computer-vision–driven Rubik’s Cube solver built around color detection, face reconstruction, and algorithmic solution generation. The system extracts cube state using calibrated imaging and solves it via a Kociemba two-phase search, which operates over the full 43,252,003,274,489,856,000 (~4.3×10¹⁹) state space of a standard 3×3 cube.

• Live Demo: Live Demo - interactive cube visualization and solver interface.
• Blog Series (PID – Project in Detail): Blog Series - detailed explanation of the color-space math, permutation constraints, cube group theory, and the intuition behind the solving algorithm.

Vision Processing and Cube State Extraction

• Performed HSV-based per-face calibration with adjustable saturation/value envelopes to stabilize under variable illumination.

• Applied contour filtering and grid isolation after morphological denoising to lock onto a valid 3×3 cell arrangement.

• Executed homography-based perspective correction and grid segmentation, assigning colors by mean-HSV dominance.

• Combined all six captures into a canonical 54-character cube state string, checked for:

  • valid center-orientation mapping,
  • edge/corner permutation parity,
  • orientation sum constraints (edges mod 2, corners mod 3).

Solution Generation and Simulation

• Used a Unity visualization environment for state verification, stepwise execution, and intermediate-move replay.

• Integrated Kociemba’s two-phase algorithm with explicit details:

  • Phase 1: reduces the cube into the H subgroup by constraining edge orientation (2¹¹ states), corner orientation (3⁷ states), and UD-slice edge placement (12 choose 4). Search explores ≈ ≈2.2×10¹⁰ possibilities but prunes aggressively using precomputed coordinate tables.
  • Phase 2: solves from H to the identity using restricted move set and coordinated distance tables over ≈ 1×10⁹ admissible states.

• Typical generated solutions fall in the 18–22 move range (quarter-turn metric), with occasional optimal-length sequences for favorable states.

• Viewer supports interactive updates, solution playback, and direct manipulation of state representations.

Repositories

Implemented a full 3D medical-imaging classification pipeline for Alzheimer’s, MCI, and cognitively normal subjects using PyTorch/MONAI.
Focused on volumetric preprocessing, stable normalization across scanners, and architecture search over 3D convolutional backbones.

• Designed a unified DICOM/NIfTI preprocessing flow with voxel-size normalization, spatial reorientation, intensity Z-scoring, Nyúl histogram standardization, and optional radiomic-feature augmentation.
• Built data transforms with 3D affine jitter, elastic deformation, anisotropic scaling, and bias-field augmentation to model scanner variability.
• Implemented Med3DNet-style 3D CNNs with custom heads: channel-progressive blocks, SE/CBAM attention, depth-scheduled 3D convolutions, and dropout tuned via Bayesian optimization.
• Used MONAI’s sliding-window inference, smart-cache loading, and mixed Gaussian/Rician noise regularization for stable training on full MRI volumes.
• Performed Bayesian hyperparameter search over learning rates, kernel schedules, convolution depths, and ensemble configurations.
• Achieved >93% accuracy on held-out structural MRI volumes with strong stability under cross-scanner shifts due to aggressive normalization and augmentation.

Tools: PyTorch • MONAI • NiBabel • 3D CNNs • Bayesian Optimization • Medical Image Preprocessing

Built and fine-tuned continuous-action PPO agents on AWS SageMaker for camera-based autonomous racing.
Focused on reward shaping, action-space optimization, and stability constraints that reduce off-track drift and maximize progress-per-step.
Achieved sub-2-minute lap times, reaching top global leaderboard ranks in 2024.

• Trained end-to-end vision policies using clipped PPO (v4) with a shallow convolutional encoder and continuous steering/speed control.
• Designed multiple reward families emphasizing centerline stability, heading agreement, curvature-aware waypoint tracking, and velocity-weighted progress.
• Used distance-band shaping (0.1/0.25/0.5× track-width thresholds) to stabilize early learning and suppress divergence near edges.
• Added steering smoothness constraints to reduce high-jerk trajectories while allowing aggressive straight-line acceleration.
• Tuned PPO hyperparameters (entropy annealing, clipping ε, GAE λ, advantage normalization) to avoid policy collapse in long-horizon tasks.
• Evaluated robustness under simulated perturbations via waypoint jitter, curvature sweeps, and speed-limit randomization.
• Final optimized agent consistently produced <2 min laps, outperforming default baselines.

Tools: AWS SageMaker • DeepRacer Simulator • Clipped PPO • Continuous RL • Policy Gradient Optimization

Repositories

A fully simulated 4-wheel autonomous robot equipped with GPS, 9-axis IMU, 2-D LiDAR, ultrasonic distance sensors, and a 2-DOF camera system (linear + rotary actuation).
Implements global-position tracking, local mapping, object detection via camera streams, and reactive obstacle avoidance with minimal control logic.
All sensing, actuation, and navigation behaviors are implemented inside the simulation stack.

• 4-wheel ground platform with independent velocity control for smooth turn/translation behavior.
• GPS provides global (x,y) estimates; IMU provides orientation & angular velocity; LiDAR provides local ranging for free-space detection.
• 2-DOF camera module (linear rail + rotary joint) models active vision for object detection and viewpoint planning.
• Distance sensors around the chassis give short-range obstacle feedback for collision-free local motion.
• Robot supports simple teleoperation mappings (↑ ↓ ← → for locomotion; W/S/A/D for camera actuation) and autonomous wandering modes.
• Designed as a baseline multi-sensor testbed for evaluating classic robotics behaviors without advanced SLAM or learning methods.

Repositories

A simulation-based control project developed for the Robotrix-2k25 finals.
A ball is shot in random directions and with varying forces, and the robot must reposition a 3-axis hoop to intercept it.
Ball position cannot be accessed directly; only two stereo cameras mounted on the backboard are available.
Ball 3D position is reconstructed via color segmentation, stereo disparity, and camera→world transforms, followed by 3D trajectory prediction and PID-driven actuator control.

Stereo Vision + 3D Reconstruction + Predictive Control Workflow

• Detect the ball using HSV color filtering on two synchronized camera frames.
• Extract pixel centroids from both sensors and compute disparity $d = x_l - x_r$.
• Recover depth using the stereo pinhole model $Z = (fB)/d$.
• Reconstruct $(X,Y,Z)$ in camera coordinates and map into world frame using fixed transforms.
• Estimate velocity from successive frames and predict future positions using projectile equations.
• Command the hoop actuators through 3 PID controllers (X, Y, Z) to align with the predicted intercept point.
• Loop at camera frame rate until shot completes.

Qualified the Round-1 of GRiD-6.0

A vision-based system for automated grocery-item quality and quantity assessment.
The solution integrates a unified dataset (multiple Roboflow sources aggregated and re-annotated) and a consolidated training run using a CNN-based detector (YOLOv7 backbone). The pipeline evaluates produce freshness, packaging correctness, text/OCR extraction, and item count/brand verification.

Core Capabilities Implemented

• Constructed a merged multi-domain dataset (FMCG, produce, OTC, personal care, household items) using Roboflow pipelines; standardized annotations across label types.
• Designed a complete smart vision quality pipeline following the GRiD specification
  • High-resolution image acquisition with normalization, light balancing, and noise suppression.
  • Preprocessing: brightness/contrast normalization, color correction, background segmentation.
  • OCR extraction using contour-guided ROI selection for brand name, pack size, label info, MRP, expiration dates.
  • Freshness scoring for fruits/vegetables via color-shift analysis, texture deviation metrics, spoilage cue detection, and geometric deformation checks.
  • Classification using deep CNN feature embeddings + auxiliary SVM for edge cases requiring shallow decision boundaries.
  • Brand recognition & count estimation using object-level shape/size features, multi-crop inference, and IR-style logical rules (simulated) as required by the event’s Use Case 3.
• Implemented text-driven quality/validity validation:
  • Extract label text and MRP/expiry-printed data.
  • Run OCR confidence filtering and text-normalization passes.
• Designed a decision engine cross-checking extracted attributes against the product database (brand, freshness index, label validity, count correctness).
• Added a continuous data logging + feedback loop as recommended in event guidelines for improving classification reliability over time.
• Submitted simulation videos demonstrating:
  • OCR output validation
  • Freshness detection on vegetables/fruits
  • Packaging/label integrity checks
  • Count & product-category recognition