Profile repository with workflows to create custom repo cards and stats for private repos, including a dynamic greeting line

CMOS inverter designed in Magic VLSI using SCMOS technology, extracted into a SPICE netlist, and simulated in ngspice. Includes layout, extraction files, and a simulation wrapper with transient ana…

This repository contains MATLAB implementations of fundamental DSP experiments, including signal processing, convolution, FFT, and filter design

USB 1.1 Device Controller Core, implemented and verified using self-checking testbenches and automated simulation scripting. The design models the digital protocol layer of a USB device, including …

Open-source Caravel SoC with RTL and testbenches, integrating BM Labs’ ReRAM-based Non-Volatile Memory (NVM) IP. Includes full SoC design flow leveraging open-source tools for synthesis, simulation…

ViSiON - Verilog for Image processing and Simulation-based Inference Of Neural Networks

Complete ASIC design flow for a Simple Inverter — from RTL (Verilog) to GDSII — using the OpenLane toolchain and the SkyWater 130nm PDK (sky130)

A hardware FIR accelerator with configurable taps and coefficients, exposing a Wishbone-Lite memory-mapped interface. Input samples are processed via a sequential MAC arch with deterministic latenc…

4-bit Ripple Carry Adder implemented using OpenROAD and a few other OpenSource EDA Tools. Demonstrates full VLSI RTL-to-layout flow with synthesis (Yosys/ABC), placement, routing, and schematic vis…

VLSI test project: 4-bit ripple carry adder with random stuck-at fault injection. Supports ATPG-based verification, fault modeling, and simulation for learning and experimentation

A multi-channel PWM SoC (wo CPU) for standalone motor ctrl on Caravel platform, w/ configurable timers, deadtime insertion, safety logic, ADC feedback & modular IPs, ideal for robotics, automotive …

8-bit ALU implemented in Verilog, designed and verified using Xilinx Vivado. RTL to GDS flow completed using OpenLane with the Sky130 PDK

Pulse Width Modulation (PWM) Generator implemented on the Caravel System-on-Chip (SoC) platform

Course Project Repository with all source files required

Planned repository for the Webots hands-on session organized by RIGNITC, designed for B24 participants

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