IP Core Library - Published and maintained by the Open Source VHDL Group

An Open-source FPGA IP Generator

Submission template for Tiny Tapeout 06 - Chisel HDL Projects

The personal, minimalist, super-fast, database free, bookmarking service - community repo

A Just-In-Time Compiler for Verilog from VMware Research

A GPU acceleration flow for RTL simulation with batch stimulus

FFT wrriten in Chisel

TangNano-4K-example project with opensource hdmi tmds implementation

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

Primary GIT Repository for the Zephyr Project

Documenting the Anlogic FPGA bit-stream format.