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Signed-off-by: Daisy Chu <daichu@nvidia.com>
Signed-off-by: Daisy Chu <daichu@nvidia.com>
Signed-off-by: Daisy Chu <daichu@nvidia.com>
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Fuse eligible Wan VAE convolutions and bias adds with cuDNN, preserving the BF16 rounding boundary before the bias. The fast path is selected automatically for supported B200 shapes and runtime; other inputs use the existing PyTorch implementation.
FastWan2.2 TI2V 5B on one B200: 704×1280, 121 frames, three DMD steps, BF16, compilation on and CUDA graphs off. Paired full-generation measurements use three prompts and six timed requests per arm per prompt on TensorRT-LLM
1.3.0rc27.dev202609150000. Both arms include the VAE norm–SiLU optimization from #19310.Validation: 14 production operator cases passed numerical checks; profiling confirms 495 fused calls per generation. Worst-prompt mean LPIPS across all 121 frames is 0.0000793 (limit 0.25). Dispatch, fallback and plan-cache unit tests pass.