RTL implementation of a full-scale elevator controller that is composed of two main modules: Controller Unit and Request Generator.

RISC-V processor supporting all forty RV32I user-level instructions. The processor is pipelined with correct hazards handling. The design was tested and verified on the Nexys A7 FPGA using Xilinx V…

Advanced Encryption Standard based cyber security C++ project that can encrypt/decrypt infinitely huge data in short time durations using Object Oriented Programming and multithreading.

RTL Implementation of a channel coding (QPSK) for a WiMAX system on a DE0-CV FPGA, using VHDL on Altera Quartus.

Parallel implementations for multiple algorithms using CUDA C on general purpose GPUs

C++ cache memory simulator that utilizes direct mapping.

C++ functional RISC-V simulator capable of tracing the execution of all 40 user-level RV32I instructions.

C++ architectural simulator capable of assessing the performance of a simplified superscalar out-of-order dual-issue 16-bit RISC processor that uses Tomasulo’s algorithm with speculation

Parking area simulator using a microcontroller, an Ethernet shield, LCD, keypad, H-bridge, DC motor, and LDR sensors.

This project can be used with MPLABX and XC8 compiler, for interfacing HC-SR04 sensors, LCD, ESP8266 and PIC16F877A

Bitwise VHDL multiplier that displays the results on an SSD in BCD