Free monospaced font with programming ligatures

Central code reposity for the common ethernet RTL modules.

A GPU-Accelerated First-Order LP Solver

Transistor level 6502 Hardware Simulation in Javascript

Graph library for graph triangulation experimentation

LibreLane Continuous Integration Designs

Official 42 norminette

Entirety of `rustc`, translated to C.

Counting until the heat death of the universe, and broadcasting the counter every second over 100Mbps ethernet.

Python/C/RTL cosimulation with Xilinx's xsim simulator

Evaluation Framework for End-to-End Analyses

Real-world automotive cause-effect chain fingerprints, a synthetic task-set generator, and 500 benchmark instances for end-to-end timing analysis.

Multiplayer CMOS Standard Cell Chips Reverse Engineering Tool

Ethernet PHY PMOD (Microchip LAN8720A PHY)

Compile Rust to Java bytecode and runnable JARs.

Yosys Open SYnthesis Suite

Build the network stack from raw bytes. 289 hands-on lessons in C and Python — from Ethernet frames to TLS 1.3

HAL – The Hardware Analyzer

fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI

Make React-Native Turbo Modules out of Rust

Xilinx Virtual Cable Implementation based on ESP8266

Beautiful Digital Timing Diagrams with Rust

Experiments in hearing

Read-only mirror of the official repo at git://sigrok.org/pulseview. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

Snappy pipeline viewer. 🥷

RP2040 - RV-3028-C7 example