Ariane is a 6-stage RISC-V CPU

The root repo for lowRISC project and FPGA demos.

Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Convolution visualizations

This is a paper list about the most important techs and some hard core knowledge about ray tracing.

Simple Path Tracer on an FPGA

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Vulkan-Sim is a GPU architecture simulator for Vulkan ray tracing based on GPGPU-Sim and Mesa.

A Vim plugin to colorize all text in the form #rrggbb or #rgb.

Indent & syntax script for Verilog and SystemVerilog

verilog filetype plugin to enable emacs verilog-mode autos

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as…

Xv6 for RISC-V

The RIFFA development repository

A template project for beginning new Chisel work

Deep Reinforcement Learning of Analog Circuit Designs

A very simple and easy to understand RISC-V core.

An open source GPU based off of the AMD Southern Islands ISA.

GPGPU microprocessor architecture

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Tcl Debug extension for VS Code

Google Research

DRAMSim2: A cycle accurate DRAM simulator

Python-based hardware modeling framework

Yosys Open SYnthesis Suite

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overa…