EDANexus
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OpenDB
OpenDB PublicForked from The-OpenROAD-Project/OpenDB
Database and Tool Framework for EDA
C++ 1
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yosys_gatemap
yosys_gatemap PublicForked from tomverbeure/yosys_gatemap
An example that shows how to map a design to a custom cell library.
Verilog
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yosys_split_ops
yosys_split_ops PublicForked from tomverbeure/yosys_split_ops
Yosys techmaps to split operations on large vectors into multiple smaller ones.
Verilog
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yosys_techmap_blog
yosys_techmap_blog PublicForked from tomverbeure/yosys_techmap_blog
Example repo for blog post
Verilog
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Repositories
- PyRTL Public Forked from UCSBarchlab/PyRTL
A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.
- atopile Public Forked from atopile/atopile
Design circuit boards with code! ✨ Get software-like design reuse 🚀, validation, version control and collaboration in hardware; starting with electronics ⚡️
- oss-cad-suite-build Public Forked from YosysHQ/oss-cad-suite-build
Multi-platform nightly builds of open source digital design and verification tools
- naja Public Forked from najaeda/naja
Structural Netlist API (and more) for EDA post synthesis flow development
- pycaliper Public Forked from adwait/pycaliper-intel
PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g., Verilog, SystemVerilog)
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