opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

IC design and development should be faster，simpler and more reliable

HDL libraries and projects

The Ultra-Low Power RISC-V Core

An Open-source FPGA IP Generator

Various HDL (Verilog) IP Cores

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

The RIFFA development repository

Bus bridges and other odds and ends

Verilog UART

AMBA bus lecture material

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

An FPGA-based FT232H/FT600 chip controller for rapid data transmission via USB. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。

FuseSoC-based SoC for VeeR EH1 and EL2

Real time face detection based on Arm Cortex-M3 DesignStart and FPGA

NES in Verilog

Open source design files for the TinyFPGA B-Series boards.

🌱 ❄️ Collection of open-source peripherals in Verilog

Verilog HDL files

An open source FPGA design for DSLogic

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using…

A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

Simple 8-bit UART realization on Verilog HDL.

8051 core

A simple Verilog SPI master / slave implementation featuring all 4 modes.

DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.

TangPrimer-25K-example project

Basic Peripheral SoC (SPI, GPIO, Timer, UART)