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The PIOC(Programmable Protocol I/O Microcontroller) of CH32X035/4/3 and CH643.

Rust 8 1 Updated Sep 5, 2024

gd32

C 5 2 Updated Sep 14, 2023

Linux driver for Intelligent Platform Management Bus (IPMB)

C 6 3 Updated Feb 14, 2025

Manchester decoding example for STM32 MCUs.

C 9 2 Updated May 14, 2023

SEGGER SystemView target sources, configurations, and RTOS patches.

C 84 17 Updated Nov 21, 2025

NES in C

Assembly 96 17 Updated Oct 31, 2022

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 2,514 323 Updated Jan 7, 2026

Send video/audio over HDMI on an FPGA

SystemVerilog 1,259 136 Updated Feb 3, 2024

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K,

Verilog 4 Updated Feb 2, 2024

Fixed-point math library with VHDL, Python and MATLAB support

VHDL 3 2 Updated Dec 8, 2025
C 2 1 Updated Mar 24, 2021

GD32F30x 工程示例代码,已移植 FreeRTOS,封装了相关代码实现,供大家参考学习

C 7 3 Updated May 10, 2022

A modern GUI library for embedded systems

C 137 30 Updated Mar 25, 2026
Verilog 1 1 Updated Apr 5, 2025

【分享】华中科技大学研究生课程资料

HTML 1 Updated Jan 11, 2021
HTML 1 Updated Apr 1, 2025

virtual debug pod for RP2040 "Raspberry Pi Pico" with no added hardware

C 422 54 Updated Aug 3, 2022

UVM verification platform for DW_apb_i2c IP core(Master Mode)

Verilog 12 4 Updated Aug 21, 2023

OpenBMC Distribution

BitBake 2,383 1,090 Updated Mar 26, 2026
RobotFramework 128 106 Updated Mar 26, 2026
C++ 8 7 Updated Mar 19, 2026

An open-source tool for controlling IPMI-enabled systems

C 1,587 409 Updated Feb 9, 2023

IPMB driver to send requests from the BlueField to the BMC on CentOS

C 6 8 Updated Sep 18, 2019

A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board

Verilog 13 7 Updated Sep 7, 2018

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

Verilog 438 48 Updated Jun 20, 2025

Open-source telemetry dashboard. Supports UART, BLE, MQTT, Modbus, CAN Bus and more.

C++ 6,732 1,011 Updated Mar 26, 2026

Verilog code for UART communication, including modules for transmitting, receiving, and baud rate generation, along with a testbench for verification.

VHDL 9 4 Updated Oct 18, 2024

Bus bridges and other odds and ends

Verilog 656 126 Updated Mar 10, 2026

A collection of debugging busses developed and presented at zipcpu.com

Verilog 43 7 Updated Jan 18, 2024

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilog 652 87 Updated Mar 26, 2026
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