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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
kyonmiriam / nestang_primer-25K
Forked from nand2mario/nestangNESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K,
open-logic / en_cl_fix
Forked from enclustra/en_cl_fixFixed-point math library with VHDL, Python and MATLAB support
XGonger / HUST-Invictus
Forked from lyandut/HUST-Invictus【分享】华中科技大学研究生课程资料
virtual debug pod for RP2040 "Raspberry Pi Pico" with no added hardware
UVM verification platform for DW_apb_i2c IP core(Master Mode)
An open-source tool for controlling IPMI-enabled systems
IPMB driver to send requests from the BlueField to the BMC on CentOS
A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
Open-source telemetry dashboard. Supports UART, BLE, MQTT, Modbus, CAN Bus and more.
Verilog code for UART communication, including modules for transmitting, receiving, and baud rate generation, along with a testbench for verification.
A collection of debugging busses developed and presented at zipcpu.com
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
sipeed / bl_mcu_sdk
Forked from bouffalolab/bouffalo_sdkbl_mcu_sdk is MCU software development kit provided by Bouffalo Lab Team for BL602/BL604, BL702/BL704/BL706 and other series of RISC-V based chips in the future.
Tool to extract nuitka compiled executables
Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit