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Vibe GPU Project

This project implements a custom SIMT (Single Instruction, Multiple Threads) GPU from scratch. It includes the SystemVerilog RTL design, a Verilator-based simulation environment, and a complete software stack ranging from an Assembler to a CUDA-like high-level frontend.

📄 Detailed Architecture Documentation

1. Hardware Architecture (RTL)

Hardware Architecture

The GPU is designed with a focus on SIMT execution, hardware-managed divergence, and pipelining. For deep technical details on the Pipeline, SIMT Stack, and Memory Hierarchy, see docs/ARCHITECTURE.md.

  • Cores: 4 Streaming Multiprocessors (SMs).
  • Execution Model: SIMT (Single Instruction, Multiple Threads).
    • Threads: 8 Threads per Warp, 4 Warps per SM (128 total threads).
    • Scheduling: Round-Robin Warp Scheduler.
  • Pipeline: 5-Stage (IF, ID, EX, MEM, WB) with Scoreboarding and Hazard Detection.
  • Memory: Unified Memory with L1 Caching and Banked Access.
  • ISA: Custom RISC-like 32-bit ISA with FP8 support.

2. Software Stack

Software Stack

We provide a vertically integrated software stack.

Level 2: Vibe CUDA Frontend (tools/vibe_cuda.py)

Write Python functions decorated with @cuda.jit. The compiler performs AST analysis, register allocation, and assembly generation.

import tools.vibe_cuda as cuda

@cuda.jit(block_dim=32)
def matmul_kernel(a, b, c):
    gid = cuda.blockIdx.x * cuda.blockDim.x + cuda.threadIdx.x
    # ... matrix multiplication logic ...
    c[gid] = acc

Level 1: Assembler (tools/assembler.py)

Directly emit instructions using Python method calls.

asm.ldi(1, 10)      # R1 = 10
asm.add(3, 1, 2)    # R3 = R1 + R2

3. Test Suite & Verification

A comprehensive test suite automates the verification of hardware features.

Running Tests

python3 tests/test_suite.py

Included Tests

  1. MatMul: Full Matrix Multiplication with random data (Verifies ALU, Loops, Memory, Address Calc).
  2. FC Layer: Fully Connected Layer with ReLU activation (Verifies Matrix-Vector Mul, Bias, Branching).
  3. VecMul: Vector Multiplication.
  4. Divergence: Nested if/else control flow (Verifies SIMT Stack and Execution Masks).
  5. Loop: for loop iteration logic.
  6. FP8: Floating-point unit verification.

4. Directory Structure

  • rtl/: SystemVerilog source code (sm_core.sv, alu.sv, simt_stack.sv, regfile.sv, etc.).
  • sim/: Verilator simulation files (main.cpp, Makefile).
  • tools/: Compiler and Assembler tools (vibe_cuda.py, assembler.py, isa.py).
  • apps/: Application kernels (app_cuda_matmul.py, app_cuda_vecmul_test.py, etc.).
  • tests/: Generated binaries (program.hex), gold references, and the test runner (test_suite.py).
  • docs/: ISA documentation.

5. Getting Started

  1. Prerequisites: Install verilator, make, python3, g++.
  2. Run a Kernel:
    # Compile and run the Matrix Multiplication example
    python3 apps/app_cuda_matmul.py
    cd sim && make run
  3. View Waveforms: The simulation generates sim_trace.vcd. Open it with GTKWave to inspect internal signals (Pipeline stages, PC, Registers).

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