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RV-RTOS8

Piveline: RV-RTOS8 logo image FreeRTOS porting on 8-stage pipelined RISC-V CPU with HDMI and keyboards

Repository Structure

  • /FPGA : Synthesizable Vivado project files on RV32 / RV64 implementations
  • /Firmware : FreeRTOS Kernel + Shell firmware source codes
  • /RTL : VerilogHDL RTL source codes for iverilog simulation

Current Progress

  • ✅ Rhealstone switch, preempt benchmark
  • 📝 Full function support for FreeRTOS and verification with other 4 Rhealstone benchmarks.

Overview

  • This repository is about implementing FreeRTOS Kernel on 8-stage pipelined bare-metal RISC-V processor from RV-IM100.
    • FreeRTOS:
      An open-source real-time operating system kernel providing preemptive scheduling, software timers, and inter-task communication for resource-constrained embedded systems.
    • RV-IM100:
      Design guidelines and performance analysis for 10 RISC-V 5- to 8-stage pipeline variants based on basic_RV32S and IMA_make_RV64, covering ISA extension scaling, pipeline-depth sweep, and 100 MHz(125) timing closure on Artix-7 FPGA.
  • To make the fully working computing system, we've also implemented HDMI display output interface with PS/2 keyboard input interface.
  • To verify the FreeRTOS implementation, we've benchmarked with Rhealstone within our original shell program.
    • Rhealstone:
      A benchmark suite for evaluating real-time operating system performance, measuring key metrics such as task switching time, preemption time, interrupt latency, semaphore shuffling, message passing, and deadlock breaking.
    • We couldn't fine the original source code of Rhealstone, so we've ported RTEMS Rhealstone to FreeRTOS.

Architecture

Core Architecture

72F8SP_core_architecture RV64IM72F_8SP Core Architecture block diagram
  • IF-IO-ID-EXR-EX-BR-MEM-WB : 8-Stage Pipeline
  • We've revised several modules for FreeRTOS support.
    • trap-exception logic modules for ECALL & timer tick interaction from FreeRTOS.
    • CSR for CLINT support
  • For more information, visit RV-IM100 repository

SoC Architecture

72F8SP_SoC_architecture 72F8SP_SoC Architecture block diagram
  • Designed CLINT module for timer tick interactions
  • Several modules added for UART TX, PS/2 keyboard input, HDMI display output

Environment

  • FPGA board
    • Digilent Nexys Video (AMD Xilinx Artix-7 XC7A200T-1SBG484C)
  • AMD Vivado 2025.2

Benchmarks

  • Rhealstone
    Table: Rhealstone-Derived Benchmark Results (FreeRTOS, 100 MHz)
Sub-benchmark RV32 (cycles/iter) RV64 (cycles/iter) RV64 Overhead
Task Switch 320 439 +37.2%
Task Preempt 1,073 1,264 +17.7%
image

Acknowledgment

Contributors

  • @T410N (Hyunwoo Kang) - Project Lead & Architecture design & Main debugging
  • @iGangs3597 (iGangs) - Shell develop & CSR modification
  • @kim0331-sketch (Jongwon Kim) - Exception/Interrupt Handling (CSR, CLINT) & Architecture block diagram
  • @DBTMDDN (Seungwoo You) - mstatus CSR Implementation & FreeRTOS Trap Logic Extension
  • @ghilmc1019 (ghilmc1019) - CLINT implementation & Trap Controller TIMER_INTERRUPT_IRQ handling logic design & Shell develop

About

FreeRTOS porting on 8-stage pipelined RISC-V CPU with HDMI and keyboards

Topics

cpu processor riscv freertos hdmi ps2 rtos risc-v microarchitecture rv32im rv64im 8-stage-pipeline riscv-freertos riscv-rtos xlen

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MIT license
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