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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.
Project Apicula 🐝: bitstream documentation for Gowin FPGAs
NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
An open source SPI flash emulator and monitor
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
A simple, basic, formally verified UART controller
FPGA-based Nintendo Entertainment System Emulator
A Hardware Description Language based on the Rust Programming Language
Open-source electrophoretics display controller. Mirror of https://gitlab.com/zephray/caster
Advanced Interface Bus (AIB) die-to-die hardware open source
A single-wire bi-directional chip-to-chip interface for FPGAs
Test of the USB3 IP Core from Daisho on a Xilinx device
Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Project template for Artix-7 based Thinpad board
Chisel translation of TangNano-4K-example/dk_video