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30 results for source starred repositories written in Verilog
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OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,345 749 Updated Dec 24, 2025

Verilog PCI express components

Verilog 1,491 379 Updated Apr 26, 2024

Verilog library for ASIC and FPGA designers

Verilog 1,377 299 Updated May 8, 2024

Source and Documentation files for USB C Industrial Camera Project, This repo contains PCB boards, FPGA , Camera and USB along with FPGA Firmware and USB Controller Firmware source.

Verilog 1,057 202 Updated Oct 22, 2023

The RIFFA development repository

Verilog 859 347 Updated Jun 11, 2024

Various HDL (Verilog) IP Cores

Verilog 855 227 Updated Jul 1, 2021

Bus bridges and other odds and ends

Verilog 612 118 Updated Apr 14, 2025

Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Verilog 608 83 Updated Dec 21, 2025

NESTang is an FPGA Nintendo Entertainment System implemented with Sipeed Tang Primer 25K, Nano 20K and Primer 20K boards

Verilog 421 48 Updated Jun 20, 2025

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Verilog 402 138 Updated Dec 17, 2025

An open source SPI flash emulator and monitor

Verilog 391 45 Updated Jul 17, 2020

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Verilog 370 73 Updated Jul 12, 2017

A simple, basic, formally verified UART controller

Verilog 319 51 Updated Jan 29, 2024

FPGA-based Nintendo Entertainment System Emulator

Verilog 269 65 Updated Jan 16, 2024

A Hardware Description Language based on the Rust Programming Language

Verilog 259 22 Updated Dec 23, 2025

Open-source electrophoretics display controller. Mirror of https://gitlab.com/zephray/caster

Verilog 243 20 Updated Sep 10, 2025

A Video display simulator

Verilog 174 22 Updated May 16, 2025

Advanced Interface Bus (AIB) die-to-die hardware open source

Verilog 144 37 Updated Sep 23, 2024

A single-wire bi-directional chip-to-chip interface for FPGAs

Verilog 125 16 Updated Jul 7, 2016

Test of the USB3 IP Core from Daisho on a Xilinx device

Verilog 100 32 Updated Oct 3, 2019
Verilog 89 44 Updated May 4, 2017

Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.

Verilog 81 18 Updated Apr 30, 2019
Verilog 69 11 Updated May 5, 2023

PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers

Verilog 64 7 Updated Apr 27, 2025

Open Component Portability Infrastructure

Verilog 62 20 Updated May 1, 2021

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.

Verilog 56 9 Updated Sep 15, 2020

Project template for Artix-7 based Thinpad board

Verilog 52 24 Updated Sep 13, 2025

Drop In USB CDC ACM core for iCE40 FPGA

Verilog 34 4 Updated Sep 5, 2021

Anlogic examples with Yosys

Verilog 10 1 Updated Dec 1, 2018

Chisel translation of TangNano-4K-example/dk_video

Verilog 3 1 Updated May 14, 2022