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Various projects for the Nexys4DDR board from Digilent
Implemented Darius IP (originally target PYNQ) of convolution and maxpool on Xilinx FPGA with SDK
Mini projects based on Xilinx Nexys 4 DDR
Implemented using a Nexys A7 board and an external 3-axis accelerometer. It displays a tilt meter onto the LEDs using the X and Z axis data.