Skip to content
View SensuiYagi's full-sized avatar

Block or report SensuiYagi

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
6 stars written in Scala
Clear filter

Chisel: A Modern Hardware Design Language

Scala 4,562 647 Updated Feb 6, 2026

Rocket Chip Generator

Scala 3,675 1,222 Updated Jan 9, 2026

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Scala 2,133 809 Updated Feb 4, 2026

(System)Verilog to Chisel translator

Scala 116 11 Updated May 20, 2022

A lightweight Ethernet MAC Controller IP for FPGA prototyping

Scala 14 1 Updated Oct 19, 2020

A simple demo that blinks an LED on the Lattice iCEstick Evaluation Kit, written in Chisel

Scala 3 Updated Jan 28, 2022